IP Library › Granted Patent US 10,847,443
Granted Patent B2
US 10,847,443 · App. 15/801,935 · Granted Nov 24, 2020

Front-to-back bonding with through-substrate via (TSV)

Inventor: Jing-Cheng Lin (Hsinchu County, TW)
Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
H01L23/481H01L21/76898H01L24/80H01L24/92H01L24/94H01L25/0657H01L25/50H01L27/0688H01L21/76224H01L2224/0401H01L2224/05025H01L2224/05124H01L2224/05147H01L2224/05563H01L2224/05564H01L2224/05572H01L2224/05573H01L2224/05582H01L2224/05647H01L2224/05666H01L2224/05681H01L2224/08147H01L2224/13H01L2224/13111H01L2224/13113H01L2224/13116H01L2224/13139H01L2224/13147H01L2224/13155H01L2224/80013H01L2224/80075H01L2224/80091H01L2224/80095H01L2224/80896H01L2224/9202H01L2224/9212H01L2224/94H01L2225/06524H01L2225/06541H01L2225/06544H01L2225/06565H01L2924/10252H01L2924/10253H01L2924/10271H01L2924/10272H01L2924/10329H01L2924/10333H01L2924/10335H01L2924/10338H01L2924/10342
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Quick Facts
Patent No.
US 10,847,443
App. No.
15/801,935
Granted
Nov 24, 2020
Kind
B2
Abstract

Methods for forming a semiconductor device structure are provided. The method includes bonding a first wafer and a second wafer, and a first transistor is formed in a front-side of the first semiconductor wafer. The method further includes thinning a front-side of the second wafer and forming a second transistor in the front-side of the second wafer.

Claims (56)

1. A method for forming a semiconductor device structure, comprising:

forming a conductive feature in a first wafer, wherein the conductive feature is formed in an insulating layer and above a first transistor;

forming a first bonding layer over the conductive feature;

forming a second bonding layer over a second wafer;

bonding the first wafer and the second wafer by bonding the first bonding layer and the second bonding layer;

thinning a front-side of the second wafer;

forming a second transistor in the front-side of the second wafer;

after forming the second transistor in the front-side of the second wafer, forming at least one first TSV in the second wafer, wherein a bottom surface of the first TSV is level with a bottom surface of the first bonding layer; and

forming a second TSV through the first wafer and the second wafer, wherein the second TSV is through the insulating layer.

2. The method as claimed in claim 1 , wherein the second TSV directly contact a redistribution (RDL) structure formed over a backside of the first wafer.

3. The method as claimed in claim 2 , further comprising:

thinning a backside of the first wafer to expose the second TSV.

4. The method as claimed in claim 1 , wherein the second TSV has a second height greater than a first height of the first TSV.

5. The method as claimed in claim 1 , further comprising:

forming an interconnect structure over the front-side of the second wafer, wherein the interconnect structure is electrically connected to the conductive feature of the first wafer.

6. The method as claimed in claim 1 , wherein the first bonding layer and the second bonding layer are made of silicon oxide, silicon oxynitride or silane oxide.

7. The method as claimed in claim 1 , wherein no devices are formed in the second wafer before the step of thinning the front-side of the second wafer.

8. A method for forming a semiconductor device structure, comprising:

bonding a first semiconductor wafer to a second semiconductor wafer by a bonding layer, wherein the bonding layer is formed between the first semiconductor wafer and the second semiconductor wafer, wherein a first transistor is formed over a front-side of the first semiconductor wafer;

forming a conductive feature in an insulating layer in the first semiconductor wafer, wherein the conductive feature is above the first transistor;

thinning a portion of the second semiconductor wafer to form an exposed surface;

forming a second transistor in the exposed surface of the second semiconductor wafer;

after forming the second transistor in the exposed surface of the second semiconductor wafer, forming a first TSV in the second semiconductor wafer, wherein the first TSV passes through the bonding layer, wherein the step of forming the conductive feature comprises forming a first surface of the conductive feature having a first portion in direct contact with the bonding layer and a second portion in direct contact with the first TSV; and

forming a second TSV through a portion of the first wafer and the second wafer, wherein the second TSV is in direct contact with the insulating layer.

9. The method as claimed in claim 8 , further comprising:

forming an interconnect structure over the second semiconductor wafer, wherein the interconnect structure is electrically connected to a conductive feature of the first semiconductor wafer through the first TSV.

10. The method as claimed in claim 9 , wherein the interconnect structure comprises a first conductive line and a second conductive line, the first conductive line has a first surface facing a top surface of the first TSV.

11. The method as claimed in claim 8 , further comprising:

forming a first redistribution (RDL) structure on a backside of the first semiconductor wafer, wherein the second TSV contacts with the first RDL structure.

12. The method as claimed in claim 11 , wherein forming the first RDL structure comprises:

forming a metal pad on a bottom surface of the second TSV;

forming an under bump metallization (UBM) layer on the metal pad; and

forming a conductive element on the UBM layer.

13. A method for forming a semiconductor device structure, comprising:

forming a first transistor in a first wafer;

forming a conductive feature in an insulating layer and above the first transistor;

forming a first bonding layer over the conductive feature;

forming a second bonding layer over a second wafer;

bonding the first bonding layer and the second bonding layer;

thinning a portion of the second wafer;

forming a second transistor in a front-side of the second wafer;

after forming the second transistor in the front-side of the second wafer, forming a first TSV through the second wafer, such that the first TSV stops at the first bonding layer;

forming a second TSV through the second wafer and a portion of the first wafer, wherein the second TSV is in direct contact with the insulating layer; and

after forming the second TSV, thinning the first wafer to expose a bottom surface of the second TSV.

14. The method as claimed in claim 13 , further comprising:

forming a first redistribution (RDL) structure on a backside of the first wafer, wherein the second TSV directly contacts with the first RDL structure.

15. The method as claimed in claim 13 , wherein the first bonding layer and the second bonding layer made of silicon oxide, silicon oxynitride or silane oxide.

16. The method as claimed in claim 13 , wherein the first TSV as a first depth, the second TSV has a second depth greater than the first depth.

17. The method as claimed in claim 13 , wherein the first TSV contacts with the conductive feature.

18. The method as claimed in claim 13 , further comprising:

forming an interconnect structure over the front-side of the second wafer, wherein the interconnect structure comprises a first conductive line and a second conductive line, the first conductive line has a first surface facing a top surface of the first TSV.

19. The method as claimed in claim 1 , further comprising:

forming a first transistor in the first wafer;

forming a conductive feature over the first transistor, such that the conductive feature has a first surface which is in direct contact with the first bonding layer and the first TSV.

20. The method as claimed in claim 8 , further comprising:

after forming the second TSV, thinning the first semiconductor wafer to expose a bottom surface of the second TSV.

Continuity (3)
Continuation 15076141 · Mar 21, 2016
Division 13943157 · Jul 16, 2013
Related Publication 20180145011A1 · May 24, 2018
Cited By (2)
US 12,653,030 US 12,685,099