Semiconductor integrated circuit device
Disclosed herein is a semiconductor integrated circuit device which can ensure sufficient power supply ability and ESD protection capability for an I/O cell without increasing the area of the semiconductor integrated circuit. In-row power supply interconnects ( 21 a to 21 d ) provided in I/O cell rows ( 10 A, 10 B) are connected to a power supply interconnect ( 23 ) provided between the I/O cell rows ( 10 A, 10 B) via power supply interconnects ( 25 a to 25 d ). The power supply interconnect ( 23 ) is thicker than the in-row power supply interconnects ( 21 a to 21 d ).
1. A semiconductor integrated circuit device, comprising:
a first I/O cell row and a second I/O cell row each including a plurality of I/O cells arranged side by side in a first direction, the first and second I/O cell rows being adjacent to each other in a second direction perpendicular to the first direction;
a first in-row power supply interconnect and a second in-row power supply interconnect extending in the first direction in a first interconnect layer, and provided in a region of the first I/O cell row and a region of the second I/O cell row, respectively, each of the first and second in-row power supply interconnects supplying a predetermined power supply potential, and the first interconnect layer being composed of a single sublayer or two or more sublayers;
a first power supply interconnect extending in the first direction in a second interconnect layer which is located above the first interconnect layer and thicker than the single sublayer or a thickest one of the two or more sublayers of the first interconnect layer, and provided in a region between the first and second I/O cell rows, the first power supply interconnect supplying the predetermined power supply potential; and
a second power supply interconnect connecting the first power supply interconnect to at least one of the first in-row power supply interconnect or the second in-row power supply interconnect.
2. The semiconductor integrated circuit device of claim 1 , wherein
the second power supply interconnect includes an interconnect extending linearly in the second direction and connecting the first power supply interconnect to both of the first and second in-row power supply interconnects.
3. The semiconductor integrated circuit device of claim 1 , wherein
the second power supply interconnect includes an interconnect having a bend.
4. The semiconductor integrated circuit device of claim 1 , wherein
the second power supply interconnect is formed in a third interconnect layer which is located above the first interconnect layer and below the second interconnect layer, and is thicker than the at least one sublayer of the first interconnect layer.
5. The semiconductor integrated circuit device of claim 4 , wherein
the second power supply interconnect has at least a portion formed in the third interconnect layer and in the second interconnect layer.
6. The semiconductor integrated circuit device of claim 1 , further comprising
a first pad and a second pad provided in the region of the first I/O cell row and the region of the second I/O cell row, respectively, the first and second pads serving as external connection pads supplying the predetermined power supply potential, wherein
the first and second pads are arranged to oppose to each other in the second direction, and connected to the second power supply interconnect.
7. The semiconductor integrated circuit device of claim 1 , wherein
each of the I/O cells in the first and second I/O cell rows includes a high power supply voltage region and a low power supply voltage region which are separated from each other in the second direction, each of the I/O cells being arranged such that the high power supply voltage region is adjacent to the first power supply interconnect.
8. The semiconductor integrated circuit device of claim 1 , wherein
a signal interconnect extending in the second direction is provided between an adjacent pair of the I/O cells.