Semiconductor device with fin field effect transistors
A semiconductor device includes a substrate with a NMOS region and a PMOS region, a device isolation layer on the substrate to define active fins, and gate patterns on the substrate to have a length direction crossing the active fins, wherein the device isolation layer includes diffusion brake regions between respective pairs of the active fins, the diffusion brake regions being disposed adjacent to each other in a width direction of the gate patterns, and wherein a width of the diffusion brake region in the NMOS region is different from a width of the diffusion brake region in the PMOS region.
1. A semiconductor device, comprising:
a substrate including a first active region and a second active region;
a device isolation layer on the substrate to define active fins on the first and second active regions, the active fins extending in a first direction;
gate patterns extending in a second direction and crossing the active fins; and
dummy gate patterns extending in the second direction,
wherein the device isolation layer includes first separation regions extending in the second direction to separate the active fins in the first direction,
wherein a width of the first separation region on the first active region is greater than a width of the first separation region on the second active region,
wherein the first separation region on the first active region includes two opposite side portions, each of which vertically overlaps a respective one of the dummy gate patterns, and
wherein an overlap area of the active fins with a closest one of the dummy gate patterns on the first active region is smaller than an overlap area of the active fins with the closest one of the dummy gate patterns on the second active region.
2. The device as claimed in claim 1 , wherein the first separation region on the second active region is interposed between the dummy gate patterns.
3. The device as claimed in claim 1 , wherein:
the device isolation layer further includes second separation regions extending in the first direction to define long sidewalls of the active fins, and the first separation regions define short sidewalls of the active fins.
4. The device as claimed in claim 1 , wherein the second separation regions are spaced apart from each other by substantially a same distance.
5. The device as claimed in claim 1 , wherein the first active region is a PMOS region and the second active region is a NMOS region.
6. The device as claimed in claim 1 , wherein the first active region is a NMOS region and the second active region is a PMOS region.
7. The device as claimed in claim 1 , wherein the device isolation layer has a top surface lower than top surfaces of the active fins, the device isolation layer exposing sidewalls of each of the active fins.
8. The device as claimed in claim 1 , wherein a pitch between the gate patterns is substantially the same as a pitch between the dummy gate patterns.
9. The device as claimed in claim 1 , wherein a pitch between the active fins on the first active region is substantially the same as a pitch between the active fins on the second active region.
10. A semiconductor device, comprising:
a substrate including a first active region and a second active region;
a device isolation layer on the substrate to define first active fins on the first active region and second active fins on the second active region;
a first gate electrode and a second gate electrode that cross the active fins; and
a first dummy gate electrode and a second dummy gate electrode that are between the first and second gate electrodes and extend parallel to the first and second gate electrodes;
wherein the device isolation layer includes a first separation region on the first active region and a second separation region on the second active region, the first and second separation regions being adjacent to each other between the first and second dummy gate electrodes,
wherein a width of the first separation region is greater than a width of the second separation region.
wherein the first separation region includes a first side portion and a second side portion opposite to the first side portion, the first and second side portions of the first separation region vertically overlapping the first and second dummy gate electrodes, respectively, and
wherein an overlap area of the first active fins with a closest one of the first and second dummy gate electrodes on the first active region is smaller than an overlap area of the second active fins with the closest one of the first and second dummy gate electrodes on the second active region.
11. The device as claimed in claim 10 , wherein:
the first and second active fins extend in a first direction,
the first separation region separates the first active fins in the first direction, and
the second separation region separates the second active fins in the first direction.
12. The device as claimed in claim 10 , wherein:
the device isolation layer further includes third separation regions defining long sidewalls of the first and second active fins,
the first separation region defines short sidewalls of the first active fins, and
the second separation region defines short sidewalls of the second active fins.
13. The device as claimed in claim 10 , wherein the first active region is a PMOS region and the second active region is a NMOS region.
14. The device as claimed in claim 10 , wherein the first active region is a NMOS region and the second active region is a PMOS region.
15. The device as claimed in claim 10 , wherein a pitch between the first active fins is substantially the same with a pitch between the second active fins.
16. A semiconductor device, comprising:
a substrate including a first active region and a second active region;
a device isolation layer on the substrate to define a first active fin on the first active region and a second active fin on the second active region, the first and second active fins extending in a first direction; and
a dummy gate electrode on edge portions of the first and second active fins and on the device isolation layer, the dummy gate electrode extending in a second direction crossing the first direction,
wherein the edge portions of the first and second active fins vertically overlap the dummy gate electrode, and
wherein an overlap area of the edge portion of the second active fin with the dummy gate electrode is greater than an overlap area of the edge portion of the first active fin with the dummy gate electrode.
17. The device as claimed in claim 16 , further comprising a gate electrode extending in the second direction and crossing the first and second active fins.
18. The device as claimed in claim 16 , wherein the device isolation layer includes:
first separation regions defining long sidewalls of the first and second active fins; and
second separation regions adjacent to the edge portions of the first and second active fins and defining short sidewalls of the first and second active fins,
wherein a width of the second separation region on the first active region is greater than a width of the second separation region on the second active region.
19. The device as claimed in claim 16 , wherein the first active region is a PMOS region and the second active region is a NMOS region.
20. The device as claimed in claim 16 , wherein the first active region is a NMOS region and the second active region is a PMOS region..