Semiconductor devices with nanowires and methods for fabricating the same
A semiconductor device may include a substrate, a first nanowire, a second nanowire, a first gate insulating layer, a second gate insulating layer, a first metal layer and a second metal layer. The first gate insulating layer may be along a periphery of the first nanowire. The second gate insulating layer may be along a periphery of the second nanowire. The first metal layer may be on a top surface of the first gate insulating layer along the periphery of the first nanowire. The first metal layer may have a first crystal grain size. The second metal layer may be on a top surface of the second gate insulating layer along the periphery of the second nanowire. The second metal layer may have a second crystal grain size different from the first crystal grain size.
1. A method for fabricating a semiconductor device, the method comprising:
providing a substrate comprising a NMOS region and a PMOS region;
forming a first nanowire in the NMOS region, and forming a second nanowire in the PMOS region;
forming a first gate insulating layer along a periphery of the first nanowire, and forming a second gate insulating layer along a periphery of the second nanowire;
forming a first metal layer on the first gate insulating layer and along the periphery of the first nanowire; and
forming a second metal layer on the second gate insulating layer and along the periphery of the second nanowire,
wherein the first metal layer and the second metal layer comprise the same material as each other, and
wherein a first thickness of the first metal layer is thicker than a second thickness of the second metal layer and is thinner than a third thickness of the first nanowire.
2. A method for fabricating a semiconductor device, the method comprising:
providing a substrate comprising a NMOS region and a PMOS region;
forming a first nanowire in the NMOS region, and forming a second nanowire in the PMOS region;
forming a first gate insulating layer along a periphery of the first nanowire, and forming a second gate insulating layer along a periphery of the second nanowire;
forming a first metal layer on the first gate insulating layer and along the periphery of the first nanowire; and
forming a second metal layer on the second gate insulating layer and along the periphery of the second nanowire,
wherein the first metal layer and the second metal layer comprise the same material as each other,
wherein a first thickness of the first metal layer is thicker than a second thickness of the second metal layer,
wherein the method further comprises forming a first gate electrode on the first metal layer and along the periphery of the first nanowire, and
wherein the first metal layer is between the first gate insulating layer and the first gate electrode.
3. The method of claim 2 , wherein forming the first gate electrode comprises forming a first fill metal that is thicker than the first metal layer.
4. The method of claim 3 , further comprising forming a second gate electrode on the second metal layer and along the periphery of the second nanowire,
wherein forming the second gate electrode comprises forming a second fill metal that is thicker than the second metal layer.
5. The method of claim 1 , further comprising:
forming a third nanowire on the first nanowire and vertically spaced apart from the first nanowire in the NMOS region;
forming a third gate insulating layer along a periphery of the third nanowire; and
forming a third metal layer on the third gate insulating layer and along the periphery of the third nanowire,
wherein a fourth thickness of the third metal layer is thicker than the second thickness of the second metal layer.
6. The method of claim 5 , wherein the first metal layer and the third metal layer are connected to each other, and are between the first nanowire and the third nanowire.
7. The method of claim 1 , further comprising forming a barrier metal layer on the first gate insulating layer before forming the first metal layer.
8. The method of claim 7 , wherein the barrier metal layer comprises a titanium nitride (TiN) layer and a tungsten (W) nucleation layer.
9. The method of claim 1 , further comprising:
performing a surface treatment of the second nanowire before forming the second metal layer, the surface treatment comprising at least one of N 2 plasma treatment, H 2 plasma treatment, Ar plasma treatment, or NH 3 plasma treatment.
10. The method of claim 9 , wherein performing the surface treatment comprises:
forming a blocking layer that covers the NMOS region and exposes the PMOS region, wherein the blocking layer extends along the periphery of the first nanowire;
performing the surface treatment using the blocking layer; and
removing the blocking layer.
11. The method of claim 1 ,
wherein the first metal layer comprises a first crystal grain size, and
wherein the second metal layer comprises a second crystal grain size smaller than the first crystal grain size.
12. The method of claim 1 ,
wherein the first metal layer is configured to apply a tensile stress to the first nanowire, and
wherein the second metal layer is configured to apply a compressive stress to the second nanowire.
13. The method of claim 1 , further comprising:
providing a difference of surface-bonding strength in the PMOS region relative to the NMOS region to slow growth of the second metal layer relative to growth of the first metal layer.
14. A method for fabricating a semiconductor device, the method comprising:
providing a substrate comprising a PMOS region, a first NMOS region, and a second NMOS region;
forming a first nanowire in the PMOS region, forming a second nanowire in the first NMOS region, and forming a third nanowire in the second NMOS region;
forming a first gate insulating layer along a periphery of the first nanowire, forming a second gate insulating layer along a periphery of the second nanowire, and forming a third gate insulating layer along a periphery of the third nanowire;
forming a first metal layer on the first gate insulating layer and along the periphery of the first nanowire, and forming a second metal layer on the third gate insulating layer and along the periphery of the third nanowire, wherein forming the first metal layer and forming the second metal layer comprises performing a selective growth method to provide different crystal grain sizes of the first metal layer and the second metal layer, respectively;
forming a first gate electrode on the first metal layer;
forming a second gate electrode that directly contacts the second gate insulating layer, on the second gate insulating layer, the second gate electrode comprising a fill metal that is thicker than the first metal layer; and
forming a third gate electrode on the second metal layer.
15. The method of claim 14 , wherein the first metal layer comprises tungsten (W).
16. The method of claim 14 ,
wherein the fill metal of the second gate electrode comprises a second fill metal, and
wherein forming the first gate electrode comprises forming a first fill metal that is thicker than the first metal layer.
17. The method of claim 14 , further comprising performing a surface treatment on the first nanowire before forming the first metal layer, such that the surface treatment decreases surface-bonding strength between the first gate insulating layer and the first metal layer.
18. The method of claim 17 , wherein the surface treatment comprises at least one of N 2 plasma treatment, H 2 plasma treatment, Ar plasma treatment, or NH 3 plasma treatment.
19. The method of claim 14 , wherein the first metal layer is configured to apply a compressive stress to the first nanowire.