Layout pattern of a static random access memory
A layout pattern of a static random access memory (SRAM) preferably includes a first inverter and a second inverter. Preferably, the first inverter includes a first gate structure extending along a first direction on a substrate, in which the first gate structure includes a gate of a first pull-up device (PL 1 ) and a gate of a first pull-down device (PD 1 ). The second inverter includes a second gate structure extending along the first direction on the substrate, in which the second gate structure includes a gate of a second pull-up device (PL 2 ) and a gate of a second pull-down device (PD 2 ) and the gate of the PD 1 is directly under the gate of the PD 2.
1. A layout pattern of a static random access memory (SRAM), comprising:
a first inverter comprising a first gate structure extending along a first direction on a substrate, wherein the first gate structure comprises a gate of a first pull-up device (PL 1 ), a gate of a first pull-down device (PD 1 ), a first long side, and a first short side; and
a second inverter comprising a second gate structure extending along the first direction on the substrate, wherein the second gate structure comprises a gate of a second pull-up device (PL 2 ), a gate of a second pull-down device (PD 2 ), a second long side, and a second short side, the first short side is aligned with the second short side, the gate of the PD 1 is directly under the gate of the PD 2 , a distance from the gate of the PD 1 to the gate of the PD 2 is less than a distance from the gate of the PL 1 to the gate of the PL 2 , and the gate of the PD 1 and the gate of the PD 2 are between the gate of the PL 1 and the gate of the PL 2 while the gate of the PL 1 is on a diagonally opposite side of the gate of the PL 2 .
2. The layout pattern of a SRAM of claim 1 , further comprising:
a gate of a first pass gate (PG 1 ) device extending along the first direction on one side of the first inverter;
a gate of a second pass gate (PG 2 ) device extending along the first direction on one side of the second inverter;
a gate of a third pass gate (PG 3 ) device extending along the first direction on another side of the first inverter; and
a gate of a fourth pass gate (PG 4 ) device extending along the first direction on another side of the second inverter.
3. The layout pattern of a SRAM of claim 2 , further comprising:
a first doped region adjacent to two sides of the gate of the PD 1 ; and
a second doped region adjacent to two sides of the gate of the PD 2 .
4. The layout pattern of a SRAM of claim 3 , wherein the first doped region is directly under the second doped region.
5. The layout pattern of a SRAM of claim 3 , further comprising:
a third doped region extending along a second direction adjacent to two sides of the gate of the PL 1 ; and
a fourth doped region extending along the second direction adjacent to two sides of the gate of the PL 2 .
6. The layout pattern of a SRAM of claim 5 , wherein the third doped region is on one side of the first doped region and the fourth doped region is on another side of the first doped region.
7. The layout pattern of a SRAM of claim 2 , further comprising a fifth doped region extending along a second direction between the gate of the PG 1 and the gate of the PG 2 .
8. The layout pattern of a SRAM of claim 2 , further comprising a sixth doped region extending along a second direction between the gate of the PG 3 and the gate of the PG 4 .
9. The layout pattern of a SRAM of claim 2 , further comprising:
a first fin-shaped structure extending along a second direction adjacent to two sides of the gate of the PD 1 ; and
a second fin-shaped structure extending along the second direction adjacent to two sides of the gate of the PD 2 .
10. The layout pattern of a SRAM of claim 9 , wherein the first fin-shaped structure is directly under the second doped region.
11. The layout pattern of a SRAM of claim 9 , further comprising:
a third fin-shaped structure extending along the second direction adjacent to two sides of the PL 1 ; and
a fourth fin-shaped structure extending along the second direction adjacent to two sides of the PL 2 .
12. The layout pattern of a SRAM of claim 11 , wherein the third fin-shaped structure is on one side of the first doped region and the fourth fin-shaped structure is on another side of the first doped region.
13. The layout pattern of a SRAM of claim 2 , further comprising a fifth fin-shaped structure extending along a second direction between the gate of the PG 1 and the gate of the PG 2 .
14. The layout pattern of a SRAM of claim 2 , further comprising a sixth fin-shaped structure extending along a second direction between the gate of the PG 3 and the gate of the PG 4 .