Method of forming a multilayer structure for a pixelated display and a multilayer structure for a pixelated display

1. A method of forming a multilayer structure for a pixelated display, the method comprising

providing a first wafer comprising first layers disposed over a first substrate, said first layers comprising non-silicon based semiconductor material;

providing a second partially processed wafer comprising silicon-based CMOS (Complementary Metal Oxide Semiconductor) devices formed in second layers disposed over a second substrate;

bonding a handle wafer to the second wafer, on a surface of the second wafer that is opposite the second substrate;

removing the second substrate from the second wafer;

bonding the second wafer on top of the first wafer, wherein a surface of the second wafer where the second substrate has been removed, is bonded to a surface of the first wafer, opposite the first substrate;

removing portions of the second layers unused by the CMOS devices, to form windows such that the first layers are exposed; and

fabricating p-n junction LEDs (Light Emitting Devices) in the first layers after the windows are formed, wherein fabricating the LEDs comprises fabricating n-contacts and p-contacts of the same height, such that the n-contacts and p-contacts are accessible at substantially the same level.

2. The method as claimed in claim 1 , wherein the CMOS devices comprises electrical contacts, the method further comprising forming tungsten plugs on the n-contacts and p-contacts, such that the tungsten plugs extend the n-contacts and p-contacts to be at the same level as the contacts of the CMOS devices.

3. The method as claimed in claim 2 , further comprising

depositing a dielectric layer on the composite wafer on a surface opposite the first substrate;

planarising the dielectric layer such that a top surface of the composite wafer is substantially level; and

connecting the CMOS devices and the LEDs with multilayer metallisation processes.

4. The method as claimed in claim 3 , wherein connecting the CMOS devices and the LEDs comprises connecting the CMOS device and the LEDs with CMOS back-end-of-line multilayer metallisation processes.

5. A method of forming a multilayer structure for a pixelated display, the method comprising

providing a first partially processed wafer comprising first layers disposed over a first substrate, said first layers comprising p-n junction LEDs (light emitting devices) formed from non-silicon based semiconductor material, the LEDs comprising n-contacts and p-contacts of the same height, such that the n-contacts and p-contacts are substantially at the same level;

providing a second partially processed wafer comprising silicon-based CMOS (Complementary Metal Oxide Semiconductor) devices formed in second layers disposed over a second substrate;

bonding a handle wafer to the second wafer, on a side of the second wafer that is opposite the second substrate;

removing the second substrate from the second wafer;

bonding the second wafer on top of the first wafer, wherein a side of the second wafer where the second substrate has been removed is bonded to a side of the first wafer opposite the first substrate, in a manner where the LEDs and CMOS devices do not substantially overlap each other, such that portions of the LEDs are exposed when unused portions of the second layers are removed.

6. The method as claimed in claim 5 , wherein the CMOS devices comprises electrical contacts, the method further comprising forming tungsten plugs on the n-contacts and p-contacts, such that the tungsten plugs extend the n-contacts and p-contacts to be at the same level as the contacts of the CMOS devices.

7. The method as claimed in claim 6 , further comprising

depositing a dielectric layer on the composite wafer on a surface opposite the first substrate;

planarising the dielectric layer such that a top surface of the composite wafer is substantially level; and

connecting the CMOS devices and the LEDs with multilayer metallisation processes.

8. The method as claimed in claim 7 , wherein connecting the CMOS devices and the LEDs comprises connecting the CMOS device and the LEDs with CMOS back-end-of-line multilayer metallisation processes.

9. A method of forming a multilayer structure for a pixelated display, the method comprising

providing a first wafer comprising first layers disposed over a first substrate, said first layers comprising non-silicon based semiconductor material;

providing a second partially processed wafer comprising silicon-based CMOS (Complementary Metal Oxide Semiconductor) devices formed in second layers disposed over a second substrate;

bonding a handle wafer to the first wafer, on a side of the first wafer that is opposite the first substrate;

removing the first substrate from the first wafer;

bonding the first wafer on top of the second wafer, wherein a side of the first wafer where the first substrate has been removed is bonded to a side of the second wafer opposite the second substrate; and

fabricating p-n junction Light Emitting Devices (LEDs) in the first layers, in a manner where the LEDs and CMOS devices do not substantially overlap each other, such that contacts of the CMOS devices are exposed when unused portions of the first layers are removed.

10. The method as claimed in claim 9 , wherein fabricating the LEDs comprises fabricating n-contacts and p-contacts of the same height, such that the n-contacts and p-contacts are substantially at the same level.

11. The method as claimed in claim 10 , wherein the CMOS devices comprises electrical contacts, the method further comprising forming tungsten plugs on the contacts of the CMOS devices, such that the tungsten plugs extend the contacts of the CMOS devices to be at the same level as the n-contacts and p-contacts.

12. The method as claimed in claim 11 , further comprising

depositing a dielectric layer on the composite wafer on a surface opposite the second substrate;

planarising the dielectric layer such that a top surface of the composite wafer is substantially level; and

connecting the CMOS devices and the LEDs with multilayer metallisation processes.

13. The method as claimed in claim 12 , wherein connecting the CMOS devices and the LEDs comprises connecting the CMOS device and the LEDs with CMOS back-end-of-line multilayer metallisation processes.

14. A method of forming a multilayer structure for a pixelated display, the method comprising

providing a first partially processed wafer comprising first layers disposed over a first substrate, said first layers comprising p-n junction LEDs (light emitting devices) formed from non-silicon based semiconductor material, the LEDs comprising n-contacts and p-contacts of the same height, such that the n-contacts and p-contacts are substantially at the same level;

providing a second partially processed wafer comprising silicon-based CMOS (Complementary Metal Oxide Semiconductor) devices formed in second layers disposed over a second substrate;

bonding a handle wafer to the first wafer, on a side of the first wafer that is opposite the first substrate;

removing the first substrate from the first wafer; and

bonding the first wafer on top of the second wafer, wherein a side of the first wafer where the first substrate has been removed is bonded to a side of the second wafer opposite the second substrate, in a manner where the LEDs and CMOS devices do not substantially overlap each other, such that contacts of the CMOS devices are exposed when unused portions of the first layers are removed.

15. The method as claimed in claim 14 , wherein the CMOS devices comprises electrical contacts, the method further comprising forming tungsten plugs on the contacts of the CMOS devices, such that the tungsten plugs extend the contacts of the CMOS devices to be at the same level as the n-contacts and p-contacts.

16. The method as claimed in claim 15 , further comprising

depositing a dielectric layer on the composite wafer on a surface opposite the second substrate;

planarising the dielectric layer such that a top surface of the composite wafer is substantially level; and

connecting the CMOS devices and the LEDs with multilayer metallisation processes.

17. The method as claimed in claim 16 , wherein connecting the CMOS devices and the LEDs comprises connecting the CMOS device and the LEDs with CMOS back-end-of-line multilayer metallisation processes.

18. The method as claimed in claim 1 , wherein the first layers comprises group III-V semiconductor material, group II-VI semiconductor material or group IV semiconductor material.

19. A multilayer structure for a pixelated display, the multilayer structure comprising

first layers comprising non-silicon based semiconductor material, the first layers comprising p-n junction LEDs (Light Emitting Devices) formed thereon, the LEDs comprises n-contacts and p-contacts of the same height, such that the n-contacts and p-contacts are accessible at substantially the same level; and

second layers formed under the first layers, the second layers comprising silicon-based CMOS (Complementary Metal Oxide Semiconductor) devices;

wherein LEDs and CMOS devices do not substantially overlap each other, such that contacts of the CMOS devices are exposed when unused portions of the first layers are removed.

20. A multilayer structure for a pixelated display, the multilayer structure comprising

first layers comprising non-silicon based semiconductor material, the first layers comprising p-n junction LEDs (Light Emitting Devices) formed thereon, the LEDs comprises n-contacts and p-contacts of the same height, such that the n-contacts and p-contacts are accessible at substantially the same level; and

second layers formed above the first layers, the second layers comprising silicon-based CMOS (Complementary Metal Oxide Semiconductor) devices;

wherein LEDs and CMOS devices do not substantially overlap each other, such that contacts of the LEDs are exposed when unused portions of the second layers are removed.

21. The method as claimed in claim 5 , wherein the first layers comprises group III-V semiconductor material, group II-VI semiconductor material or group IV semiconductor material.

22. The method as claimed in claim 9 , wherein the first layers comprises group III-V semiconductor material, group II-VI semiconductor material or group IV semiconductor material.

23. The method as claimed in claim 14 , wherein the first layers comprises group III-V semiconductor material, group II-VI semiconductor material or group IV semiconductor material.