Gate-all-around (GAA) transistors with nanowires on an isolation pedestal
Strained gate-all-around semiconductor devices formed on globally or locally isolated substrates are described. For example, a semiconductor device includes a semiconductor substrate. An insulating structure is disposed above the semiconductor substrate. A three-dimensional channel region is disposed above the insulating structure. Source and drain regions are disposed on either side of the three-dimensional channel region and on an epitaxial seed layer. The epitaxial seed layer is composed of a semiconductor material different from the three-dimensional channel region and disposed on the insulating structure. A gate electrode stack surrounds the three-dimensional channel region with a portion disposed on the insulating structure and laterally adjacent to the epitaxial seed layer.
1. A semiconductor device, comprising:
a semiconductor substrate;
an isolation pedestal disposed above the semiconductor substrate, the isolation pedestal having a unitary body with a non-planar uppermost surface;
a three-dimensional channel region disposed above the isolation pedestal;
one or more nanowires disposed in a vertical arrangement above the three-dimensional channel region;
source and drain regions disposed on either side of the three-dimensional channel region, wherein the source and drain regions are disposed on an epitaxial seed layer, the epitaxial seed layer comprising a semiconductor material different from the three-dimensional channel region and disposed on the non-planar uppermost surface of the isolation pedestal; and
a gate electrode stack surrounding the three-dimensional channel region with a portion disposed on the non-planar uppermost surface of the isolation pedestal, wherein the gate electrode stack further surrounds a channel region of each of the one or more nanowires.
2. The semiconductor device of claim 1 , further comprising:
a pair of insulating spacers, one spacer disposed between the gate electrode stack and the source region, and the other spacer disposed between the gate electrode stack and the drain region, wherein the epitaxial seed layer extends underneath each of the pair of spacers.
3. The semiconductor device of claim 1 , further comprising:
a pair of conducting contacts, one contact disposed on and partially surrounding the source region, and the other contact disposed on and partially surrounding the drain region.
4. A semiconductor structure, comprising:
a semiconductor substrate;
an isolation pedestal above the semiconductor substrate, the isolation pedestal having a unitary body with a non-planar uppermost surface;
a semiconductor body above the isolation pedestal;
one or more nanowires disposed in a vertical arrangement above the semiconductor body;
a first source or drain region at a first side of the semiconductor body;
a second source or drain region at a second side of the semiconductor body, the second side opposite the first side;
a gate electrode stack completely surrounding the semiconductor body, and wherein a portion of the gate electrode stack is on the non-planar uppermost surface of the isolation pedestal, wherein the gate electrode stack further surrounds a channel region of each of the one or more nanowires;
a first conducting contact on and at least partially surrounding the first source or drain region; and
a second conducting contact on and at least partially surrounding the second source or drain region, wherein the first conducting contact is completely surrounding the first source or drain region, and the second conducting contact is completely surrounding the second source or drain region.
5. The semiconductor structure of claim 4 , wherein a portion of the first conducting contact and a portion of the second conducting contact is on the non-planar uppermost surface of the isolation pedestal.
6. The semiconductor structure of claim 4 , further comprising:
a first insulating spacer between a first side of the gate electrode stack and the first source or drain region; and
a second insulating spacer between a second side of the gate electrode stack and the second source or drain region, the second side of the gate electrode stack opposite the first side of the gate electrode stack.
7. A semiconductor device, comprising:
a semiconductor substrate;
an isolation pedestal disposed above the semiconductor substrate, the isolation pedestal having a unitary body with a non-planar uppermost surface;
a three-dimensional channel region disposed above the isolation pedestal;
a nanowire above the three-dimensional channel region;
source and drain regions disposed on either side of the three-dimensional channel region and on either side of the nanowire, wherein the source and drain regions are disposed on an epitaxial seed layer, the epitaxial seed layer comprising a semiconductor material different from the three-dimensional channel region and disposed on the non-planar uppermost surface of the isolation pedestal; and
a gate electrode stack surrounding the three-dimensional channel region with a portion disposed on the non-planar uppermost surface of the isolation pedestal, wherein the gate electrode stack further surrounds a channel region of the nanowire.
8. The semiconductor device of claim 7 , further comprising:
a pair of insulating spacers, one spacer disposed between the gate electrode stack and the source region, and the other spacer disposed between the gate electrode stack and the drain region, wherein the epitaxial seed layer extends underneath each of the pair of spacers.
9. The semiconductor device of claim 7 , further comprising:
a pair of conducting contacts, one contact disposed on and partially surrounding the source region, and the other contact disposed on and partially surrounding the drain region.
10. A semiconductor device, comprising:
a semiconductor substrate;
an isolation pedestal disposed above the semiconductor substrate, the isolation pedestal having a unitary body with a non-planar uppermost surface;
a three-dimensional channel region disposed above the isolation pedestal;
one or more nanowires disposed in a vertical arrangement above the three-dimensional channel region;
source and drain regions disposed on either side of the three-dimensional channel region;
a gate electrode stack surrounding the three-dimensional channel region with a portion disposed on the non-planar uppermost surface of the isolation pedestal, wherein the gate electrode stack further surrounds a channel region of each of the one or more nanowires; and
a pair of conducting contacts, one contact disposed on and surrounding the source region, and the other contact disposed on and surrounding the drain region, wherein a portion of each of the pair of contacts is disposed on the non-planar uppermost surface of the isolation pedestal.
11. A semiconductor device, comprising:
a semiconductor substrate;
an isolation pedestal disposed above the semiconductor substrate, the isolation pedestal having a unitary body with a non-planar uppermost surface;
a three-dimensional channel region disposed above the isolation pedestal;
a nanowire above the three-dimensional channel region;
source and drain regions disposed on either side of the three-dimensional channel region and on either side of the nanowire;
a gate electrode stack surrounding the three-dimensional channel region with a portion disposed on the non-planar uppermost surface of the isolation pedestal, wherein the gate electrode stack further surrounds a channel region of the nanowire; and
a pair of conducting contacts, one contact disposed on and surrounding the source region, and the other contact disposed on and surrounding the drain region, wherein a portion of each of the pair of contacts is disposed on the non-planar uppermost surface of the isolation pedestal.