Vertical integration scheme and circuit elements architecture for area scaling of semiconductor devices
Vertical integration schemes and circuit elements architectures for area scaling of semiconductor devices are described. In an example, an inverter structure includes a semiconductor fin separated vertically into an upper region and a lower region. A first plurality of gate structures is included for controlling the upper region of the semiconductor fin. A second plurality of gate structures is included for controlling the lower region of the semiconductor fin. The second plurality of gate structures has a conductivity type opposite the conductivity type of the first plurality of gate structures.
1. An inverter structure, comprising:
an upper semiconductor body vertically over and isolated from a lower semiconductor body;
a first gate structure for controlling the upper semiconductor body, the first gate structure having a first conductivity type; and
a second gate structure for controlling the lower semiconductor body, the second gate structure having a second conductivity type, the second conductivity type of the second gate structure opposite the first conductivity type of the first gate structure, wherein the second gate structure is separate and distinct from the first gate structure.
2. The inverter structure of claim 1 , wherein the first gate structure and the second gate structure are separated by an insulating layer.
3. The inverter structure of claim 1 , wherein the first gate structure and the second gate structure form a P/N junction.
4. The inverter structure of claim 1 , wherein the first gate structure is a PMOS gate structure, and the second gate structure is an NMOS gate structure.
5. The inverter structure of claim 1 , wherein the first gate structure is disposed over a top surface of the upper semiconductor body and along sidewalls of the upper semiconductor body, and wherein the second gate structure is disposed along sidewalls of the lower semiconductor body.
6. The inverter structure of claim 5 , wherein the second gate structure is further disposed below a bottom surface of the lower semiconductor body.
7. A pass gate structure, comprising:
an upper semiconductor body vertically over and isolated from a lower semiconductor body;
a first gate structure for controlling the upper semiconductor body, the first gate structure having a first conductivity type; and
a second gate structure for controlling the lower semiconductor body, the second gate structure having a second conductivity type, the second conductivity type of the second gate structure the same as the first conductivity type of the first gate structure, wherein the second gate structure is separate and distinct from the first gate structure.
8. The pass gate structure of claim 7 , wherein the upper semiconductor body and the lower semiconductor body are separated by an insulating layer.
9. The pass gate structure of claim 7 , wherein the first gate structure and the second gate structure are separated by an insulating layer.
10. The pass gate structure of claim 7 , wherein the first gate structure is an NMOS gate structure, and the second gate structure is an NMOS gate structure.
11. The pass gate structure of claim 7 , wherein the first gate structure is disposed over a top surface of the upper semiconductor body and along sidewalls of the upper semiconductor body, and wherein the second gate structure is disposed along sidewalls of the lower semiconductor body.
12. The pass gate structure of claim 11 , wherein the second gate structure is further disposed below a bottom surface of the lower semiconductor body.