Real-time input/output bandwidth estimation
A bandwidth estimation method is disclosed for measuring memory bandwidth consumption or the bandwidth consumption of any I/O bus in real time on a computer system without the use of hardware counters. The bandwidth estimation method, designed to run in isolation on a core in a multi-core computer system, generates temporally sequential and spatially random accesses to a bus such as the memory bus and reports the average latency per request. Using a pre-calculated latency-bandwidth relationship, the bandwidth on the bus is calculated and reported at runtime for every latency sample. The bandwidth estimation method allows profiling processors and computer systems in real time to determine the amount of memory or I/O traffic they are using while running a workload.
1. An apparatus comprising:
a processor comprising a plurality of cores, the plurality of cores comprising a first core and remaining cores;
memory coupled to the processor by a bus, the memory comprising instructions executable by the processor which, when executed, cause the processor to:
inject, via the plurality of cores, a predetermined amount of traffic onto the bus;
determine a dependency between latency and bandwidth of the bus based on the predetermined amount of traffic;
generate a function that, given a latency, will return an associated bandwidth based on the dependency;
execute, via the remaining cores, one or more workloads;
generate, by the first core, a plurality of memory accesses via the bus; and
calculate the bandwidth of the bus consumed by the one or more workloads based in part on the plurality of memory accesses and the function.
2. The apparatus of claim 1 , further comprising instructions which, when executed by the processor, cause the processor to:
read an effective latency of the bus;
generate a graph plotting a curve of bandwidth versus latency of the bus;
generate an inverse of the graph, the inverse of the graph plotting a second curve of latency versus bandwidth of the bus; and
express the second curve in mathematical form.
3. The apparatus of claim 1 , further comprising instructions which, when executed by the processor, cause the processor to traverse a linked list to generate the plurality of memory accesses.
4. The apparatus of claim 3 , wherein the linked list is a circular linked list.
5. The apparatus of claim 3 , wherein the linked list is an array of absolute indexes representing a next element to be visited in the traversal.
6. The apparatus of claim 3 , wherein the linked list is an array of relative indexes representing a next element to be visited in the traversal.
7. The apparatus of claim 1 , further comprising instructions which, when executed by the processor, cause the processor to:
determine a cache size of a cache coupled to the processor; and
calculate a linked list size based on the cache size.
8. The apparatus of claim 3 , wherein the plurality of memory accesses is temporally sequential and spatially random.
9. A method comprising:
injecting, via a plurality of cores of a processor, a predetermined amount of traffic onto a memory bus, the memory bus to couple a memory to the processor, the plurality of cores comprising a first core and remaining cores;
determining a dependency between latency and bandwidth of the memory bus based on the predetermined amount of traffic;
generating a function that, given a latency, will return an associated bandwidth based on the dependency;
executing, via the remaining cores, one or more workloads;
generating, by the first core, a plurality of accesses to the memory via the memory bus; and
calculating the bandwidth of the memory bus consumed by the one or more workloads based in part on the plurality of accesses to the memory and the function.
10. The method of claim 9 , further comprising:
reading an effective latency of the memory bus;
generating a graph plotting a curve of bandwidth versus latency of the memory bus;
generating an inverse of the graph, the inverse of the graph plotting a second curve of latency versus bandwidth of the memory bus; and
expressing the second curve in mathematical form.
11. The method of claim 9 , further comprising traversing a linked list to generate the plurality of memory accesses, wherein the memory accesses are temporally sequential and spatially random.
12. The method of claim 11 , wherein the linked list is a circular linked list, an array of absolute indexes, or an array of relative indexes.
13. The method of claim 9 , further comprising:
determining a cache size of a cache coupled to the processor; and
calculating a linked list size based on the cache size.
14. At least one non-transitory machine-readable storage medium comprising instructions that, when executed by a processor, cause the processor to:
inject, via a plurality of cores of the processor, a predetermined amount of traffic onto a bus coupling the processor to a device, the plurality of cores further comprising a first core and remaining cores;
determine a dependency between latency and bandwidth of the bus based on the predetermined amount of traffic;
generate a function that, given a latency, will return an associated bandwidth based on the dependency;
execute, via the remaining cores, one or more workloads;
generate, by the first core, a plurality of accesses to the device via the bus; and
calculate the bandwidth of the bus consumed by the one or more workloads based in part on the plurality of accesses to the device and the function.
15. The at least one non-transitory machine-readable storage medium of claim 14 , further comprising instructions that cause the processor to:
read an effective latency of the bus;
generate a graph plotting a curve of the bandwidth versus latency of the bus; and
generate an inverse of the graph, the inverse of the graph plotting a second curve of latency versus bandwidth of the bus.
16. The at least one non-transitory machine-readable storage medium of claim 15 , further comprising instructions that cause the processor to express the second curve in mathematical form.
17. The at least one non-transitory machine-readable storage medium of claim 16 , further comprising instructions that cause the processor to traverse a linked list to generate the plurality of accesses to the device, wherein the plurality of accesses to the device is temporally sequential and spatially random.
18. The at least one non-transitory machine-readable storage medium of claim 17 , further comprising instructions that cause the processor to:
determine a cache size of a cache coupled to the processor; and
calculate a linked list size based on the cache size.
19. The at least one non-transitory machine-readable storage medium of claim 14 , further comprising instructions that cause the processor to:
inject the predetermined amount of traffic onto a memory bus coupling the processor to a memory; and
generate the plurality of accesses to the memory via the memory bus;
wherein the calculated bandwidth is of the memory bus.
20. The at least one non-transitory machine-readable storage medium of claim 14 , further comprising instructions that cause the processor to:
inject the predetermined amount of traffic onto an input/output (I/O) bus coupling the processor to an I/O device; and
generate the plurality of accesses to the I/O device via the I/O bus;
wherein the calculated bandwidth is of the I/O bus.