IP Library › Granted Patent US 10,854,474
Granted Patent B2
US 10,854,474 · App. 16/842,376 · Granted Dec 1, 2020

Pre-cut plating lines on lead frames and laminate substrates for saw singulation

Inventors: Erma Gallenero Gardose (Baguio, PH); Liya Flores Aquino (Baguio, PH)
Assignee: TEXAS INSTRUMENTS INCORPORATED
H01L21/4842H01L21/4825H01L21/4828H01L23/4952H01L23/49503H01L23/49537
View Patent ↗
Loading inventors, assignments & file history…
Monitor This Case
Get email alerts when status or documents change.
Order Certified Copies
Most orders are placed with the USPTO same day — all within 24 business hours.
Order via The Patent Place →
Pre-filled with this patent's details
Quick Facts
Patent No.
US 10,854,474
App. No.
16/842,376
Granted
Dec 1, 2020
Kind
B2
Abstract

Described herein is a technology or a method for pre-fabricating pre-cut plating lines on a lead frame with use of a pre-cut etchback process to minimize burrs during a semiconductor package singulation process. A package includes: a chip, and a lead frame that mounts the chip. The lead frame further includes pre-fabricated pre-cut plating lines that are etched back on the lead frame to form an opening slot on a periphery of the lead frame. The opening slot allows a saw blade to cut through a prepreg material, without touching or cutting a conductive material of the lead frame.

Claims (35)

1. A method of forming a semiconductor package comprising:

an etchback process on a lead frame that comprises:

forming a stack including a prepreg material, a conductive layer, and a solder mask on a lead frame;

exposing a top surface of the prepreg material; and

creating pre-cut plating lines;

mounting a chip on the lead frame;

making electrical connections from the chip to leads on the lead frame; and

cutting through the pre-cut plating lines, wherein an edge of the semiconductor package after cutting, includes a portion of the prepreg material exposed in a slot between an edge of the lead and the edge of the semiconductor package.

2. The method of claim 1 , wherein the etchback process further comprises:

patterning a masking layer on the stack; and

forming a mask opening on the masking layer.

3. The method of claim 1 , wherein creating pre-cut plating lines comprises etching back the solder mask and the conductive layer within the formed mask opening.

4. The method of claim 2 , wherein exposing a top surface of the prepreg material comprises dissolving the masking layer.

5. The method of claim 1 , wherein the conductive layer includes a copper layer that is laminated on an insulating material.

6. The method of claim 1 , wherein each of the pre-fabricated pre-cut plating lines includes a “U” shaped opening slot.

7. The method of claim 6 , wherein the opening slot includes a width wider than a width of a saw blade that is used for cutting.

8. The method of claim 5 , wherein the conductive layer includes plating lines that extend bonding wires of the electrical connection from the chip.

9. The method of claim 1 , wherein each of the pre-fabricated pre-cut plating lines includes the conductive layer etched completely until the top surface of the prepreg material.

10. A method of forming a semiconductor package comprising:

an etchback process on a lead frame that comprises:

forming a stack of prepreg material, a conductive layer, and a solder mask;

patterning a masking layer on the stack;

forming a mask opening on the masking layer;

etching back the solder mask and the conductive layer within the formed mask opening to expose a top surface of the prepreg material; and

dissolving the masking layer, thereby creating pre-cut plating lines;

mounting a chip on the lead frame;

making electrical connections from the chip to leads on the lead frame; and

cutting through the etched back pre-fabricated pre-cut plating lines.

11. The method of claim 10 , wherein the conductive layer includes a copper layer that is laminated on an insulating material.

12. The method of claim 10 , wherein each of the pre-fabricated pre-cut plating lines includes a “U” shaped opening slot.

13. The method of claim 12 , wherein the opening slot includes a width wider than a width of a saw blade that is used for cutting.

14. The method of claim 10 , wherein each of the pre-fabricated pre-cut plating lines includes a length that traverses the conductive layer on the lead frame.

15. The method of claim 14 , wherein the conductive layer includes plating lines that extend bonding wires of the electrical connection from the chip.

16. The method of claim 10 , wherein each of the pre-fabricated pre-cut plating lines includes the conductive layer etched completely until the top surface of the prepreg material.

17. The method of claim 10 , wherein each of the pre-fabricated pre-cut plating lines includes a longitudinal opening slot that includes trench sidewalls and a surface of a prepreg material.

Continuity (2)
Division 16002963 · Jun 7, 2018
Related Publication 20200234975A1 · Jul 23, 2020
Cited By (1)
US 12,745,676