Microelectronic devices including two contacts
A memory device with a dielectric layer or an air gap between contacts and a method of making the same are disclosed. The method comprises a series of steps including forming a plurality of conductive lines having trenches therebetween; forming a contact layer in the trench; and forming a dielectric layer interposed in the contact layer and configured to divide the contact layer into two contacts. The method also comprises removing the dielectric layer to form a space and forming a cap layer over the two contacts to form an air gap therein. The method further comprises forming a second air gap between the conductive line and the two contacts.
1. A microelectronic device, comprising:
a base material;
shallow trench isolation regions located in the base material;
gate structures located adjacent one another on the base material, the gate structures extending in a first horizontal direction and having trenches extending laterally therebetween;
two contacts located in individual trenches extending in the first horizontal direction between the adjacent gate structures, the two contacts laterally adjacent one another and aligned in a straight line in a second horizontal direction between the adjacent gate structures, wherein upper surfaces of each of the gate structures and the two contacts are substantially coplanar with one another; and
a cap material located over the gate structures and the two contacts to define a first air gap located over one of the shallow trench isolation regions and only between the two contacts and to define a second air gap located between one of the gate structures and one of the two contacts.
2. The microelectronic device of claim 1 , wherein at least one of the first air gap and the second air gap is filled with a gaseous material.
3. The microelectronic device of claim 2 , wherein the gaseous material comprises air.
4. The microelectronic device of claim 1 , wherein at least one of the first air gap and the second air gap comprises a vacuum.
5. The microelectronic device of claim 1 , wherein the base material comprises a cell unit comprising a first active region and a second active region therein.
6. The microelectronic device of claim 5 , wherein one of the gate structures is electrically connected to the first active region.
7. The microelectronic device of claim 5 , wherein each of the two contacts is electrically connected to the second active region of a respective cell unit.
8. The microelectronic device of claim 1 , further comprising a dielectric material on sidewalls of the two contacts.
9. The microelectronic device of claim 1 , further comprising a second dielectric material on sidewalls of the gate structures.
10. The microelectronic device of claim 1 , wherein the first air gap and the second air gap are aligned in a straight line in the second horizontal direction between the adjacent gate structures.
11. A microelectronic device, comprising:
shallow trench isolation regions in a base material;
recessed gate structures located in the base material, wherein two of the recessed gate structures are located between adjacent shallow trench isolation regions;
additional gate structures located adjacent one another on the base material and extending in a first horizontal direction;
two contacts located within an opening extending in the first horizontal direction between the adjacent additional gate structures, the two contacts laterally adjacent one another and aligned in a straight line in a second horizontal direction between the adjacent additional gate structures; and
a single cap material located directly over the additional gate structures and the two contacts to define a first space comprising a first air gap located over one of the shallow trench isolation regions and only between the two contacts and to define a second space comprising a second air gap located between one of the additional gate structures and one of the two contacts.
12. The microelectronic device of claim 11 , further comprising:
a first dielectric material located on sidewalls of each of the additional gate structures; and
a second dielectric material located on sidewalls of each of the two contacts, wherein each of the first dielectric material, the second dielectric material, and the cap material comprise the same material with no boundaries therebetween.
13. The microelectronic device of claim 11 , wherein the first space is located over one of the shallow trench isolation regions, the shallow trench isolation regions being devoid of gate structures.
14. A microelectronic device, comprising:
shallow trench isolation regions in a base material;
gate structures located adjacent one another on the base material and extending in a first horizontal direction;
two contacts located within an opening extending in the first horizontal direction between the adjacent additional gate structures, the two contacts laterally adjacent one another and aligned in a straight line in a second horizontal direction between the adjacent gate structures; and
a cap material located over the gate structures and the two contacts to define a first space comprising a first air gap located over one of the shallow trench isolation regions and only between the two contacts and to define a second space comprising a second air gap located between one of the gate structures and one of the two contacts, wherein the first air gap is separated from the base material by a dielectric material and the second air gap is in direct physical contact with the base material.
15. The microelectronic device of claim 11 , wherein the second space is located over one of the recessed gate structures.
16. The microelectronic device of claim 11 , further comprising a third space located in an upper region of at least some of the recessed gate structures, wherein the recessed gate structures comprise multi-layer structures.
17. The microelectronic device of claim 11 , further comprising first active regions and second active regions in the base material, wherein:
the first active regions are laterally spaced between adjacent recessed gate structures; and
the second active regions are laterally spaced between one of the recessed gate structures and one of the shallow trench isolation regions with each of the shallow trench isolation regions being bordered by two of the second active regions.
18. The microelectronic device of claim 17 , wherein individual additional gate structures are located over the first active regions and each of the two contacts are located over respective second active regions.
19. The microelectronic device of claim 17 , wherein one of the first active regions or the second active regions comprises source regions, and the other of the first active regions or the second active regions comprises drain regions.