IP Library › Granted Patent US 10,854,803
Granted Patent B2
US 10,854,803 · App. 16/842,716 · Granted Dec 1, 2020

Manufacturing method of light emitting device package structure with circuit redistribution structure

Inventors: Pei-Wei Wang (Taipei, TW); Cheng-Ta Ko (Taipei, TW); Yu-Hua Chen (Hsinchu, TW); De-Shiang Liu (Taoyuan, TW); Tzyy-Jang Tseng (Hsinchu, TW)
Assignee: UNIMICRON TECHNOLOGY CORP.
H01L33/62H01L2933/0033
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Quick Facts
Patent No.
US 10,854,803
App. No.
16/842,716
Granted
Dec 1, 2020
Kind
B2
Abstract

A manufacturing method of a light emitting device package structure is provided. The method includes following operations: (i) providing a circuit redistribution structure; (ii) providing a first substrate; (iii) forming a circuit layer structure over the first substrate, wherein the circuit layer structure includes a first circuit layer; (iv) before or after operation (iii), placing a light emitting device between the first substrate and the circuit layer structure or over the circuit layer structure, wherein the light emitting device is electrically connected with the first circuit layer; and (v) placing the circuit redistribution structure over the light emitting device, wherein the circuit redistribution structure includes a first redistribution layer, a second redistribution layer, and a chip, and the first redistribution layer includes a second circuit layer and a conductive contact that contacts the second circuit layer.

Claims (16)

1. A manufacturing method of a light emitting device package structure, comprising following operations:

(i) providing a circuit redistribution structure;

(ii) providing a first substrate;

(iii) forming a circuit layer structure over the first substrate, wherein the circuit layer structure includes a first circuit layer;

(iv) before or after operation (iii), placing a light emitting device between the first substrate and the circuit layer structure or over the circuit layer structure, wherein the light emitting device is electrically connected with the first circuit layer; and

(v) placing the circuit redistribution structure over the light emitting device, wherein the circuit redistribution structure includes a first redistribution layer, a second redistribution layer, and a chip, and the first redistribution layer includes a second circuit layer and a conductive contact that contacts the second circuit layer, wherein the second circuit layer is electrically connected with the first circuit layer through a conductive connector, and the second redistribution layer includes a third circuit layer that contacts the conductive contact, and the third circuit layer is electrically connected with the chip.

2. The manufacturing method of claim 1 , wherein operation (i) includes the following sub-operations:

(a) forming the first redistribution layer over a second substrate;

(b) forming the second redistribution layer over the first redistribution layer;

(c) placing the chip over the second redistribution layer; and

(d) peeling off the second substrate to expose the second circuit layer to form the circuit redistribution structure.

3. A manufacturing method of a light emitting device package structure, comprising following operations:

(i) providing a circuit redistribution structure having a substrate, a first redistribution layer, and a second redistribution layer, wherein the first redistribution layer is disposed over the substrate, and the first redistribution layer includes a first circuit layer and a conductive contact that contacts the first circuit layer; wherein the second redistribution layer is disposed over the first redistribution layer, and the second redistribution layer includes a second circuit layer that contacts the conductive contact;

(ii) placing a light emitting device over the second redistribution layer, wherein the light emitting device is electrically connected with the second circuit layer;

(iii) peeling off the substrate to expose the first circuit layer before or after operation (ii); and

(iv) placing a chip below the first redistribution layer, wherein the chip is electrically connected with the first circuit layer.

Assignments (1)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Apr 8, 2020
From: WANG, PEI-WEI; KO, CHENG-TA; CHEN, YU-HUA; LIU, DE-SHIANG; TSENG, TZYY-JANG
To: UNIMICRON TECHNOLOGY CORP.
Reel/Frame 052337/0506 →
Priority Claims (1)
TW 107122835 A · Jul 2, 2018 · national
Continuity (2)
Division 16140563 · Sep 25, 2018
Related Publication 20200235272A1 · Jul 23, 2020