IP Library › Granted Patent US 10,861,538
Granted Patent B2
US 10,861,538 · App. 16/430,720 · Granted Dec 8, 2020

Sensor device with resistive memory for signal compression and reconstruction

Inventors: Manuel Le Gallo-Bourdeau (Zurich, CH); Abu Sebastian (Adliswil, CH); Giovanni Cherubini (Rueschlikon, CH)
Assignee: International Business Machines Corporation
G11C13/0004G06F17/10G06F17/16G11C7/1006G11C13/0002G11C13/004G11C13/0064G11C13/0069H03M7/30H03M7/3062H04N5/335H04N5/378A61B5/0033A61B5/7203A61B5/726A61B2560/0475G06K9/40G06T9/00G11C2213/15G11C2213/77G11C2213/79H03M1/12
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Quick Facts
Patent No.
US 10,861,538
App. No.
16/430,720
Granted
Dec 8, 2020
Kind
B2
Abstract

A sensor device comprising a computational memory and electronic circuitry. The sensor device is configured to receive an input signal, to compress the input signal into a compressed signal and to compute a reconstructed signal from the compressed signal. The electronic circuitry is configured to perform a reconstruction algorithm to compute the reconstructed signal. The computational memory is configured to compute the compressed signal and partial results of the reconstruction algorithm. A related method and a related design structure may be provided.

Claims (64)

1. A sensor device comprising

a computational memory, the computational memory comprising at least two programmable resistance states; and

electronic circuitry;

the sensor device being configured to

receive an input signal;

compress the input signal into a compressed signal; and

compute a reconstructed signal from the compressed signal;

wherein the electronic circuitry is configured to perform a reconstruction algorithm to compute the reconstructed signal; and

the computational memory is configured to compute the compressed signal and partial results of the reconstruction algorithm.

2. A sensor device according to claim 1 , wherein

the computational memory comprises at least one memristive array comprising a plurality of resistive memory elements, wherein the memristive array comprises a plurality of row lines and a plurality of columns lines, wherein the plurality of row lines extend in a first x-y-plane and the plurality of column lines extend in a second x-y plane, wherein the first x-y plane is arranged in a vertical z-direction with respect to the second x-y-plane.

3. A sensor device according to claim 2 , wherein

the electronic circuitry is configured to

apply programming signals to the resistive memory elements to program conductance values as a measurement matrix; and

the computational memory is configured to

compress the input signal by performing a matrix-vector multiplication of the input signal with the measurement matrix; and

compute the partial results of the reconstruction algorithm by performing matrix-vector multiplications with the measurement matrix.

4. A sensor device according to claim 3 , wherein the electronic circuitry is configured to program the conductance values of the resistive memory elements by an iterative program and verify procedure.

5. A sensor device according to claim 2 , wherein

the memristive array further comprises

a plurality of junctions arranged between the plurality of row lines and the plurality of column lines, wherein each junction comprises a programmable resistive memory element.

6. A sensor device according to claim 5 , wherein

the electronic circuitry comprises a readout circuit configured to

apply read voltages to the row lines and/or column lines of the memristive array;

read out current values of the row lines and/or column lines of the memristive array; wherein

the read voltages represent vector values of a vector of a matrix-vector multiplication; and

the current values represent result values of vector elements of a product vector of the matrix-vector multiplications.

7. A sensor device according to claim 5 , wherein the plurality of junctions comprise a serial arrangement of a resistive memory element and a transistor.

8. A sensor device as claimed in claim 2 , wherein the resistive memory elements are one of Phase change memory (PCM) elements, Conductive bridge resistive memory elements, Metal-oxide resistive random access memory (RRAM) elements, Magneto-resistive random access memory (MRAM) elements, Ferroelectric random access memory (FeRAM) elements, optical memory elements, and a system device, the system device comprising transistors, resistors, capacitors, and/or inductors configured to jointly emulate a behavior of a resistive memory element.

9. A sensor device as claimed in claim 8 , wherein the resistive memory elements are phase change memory elements and wherein the device is configured to:

apply a Reset-pulse to the phase change memory elements in order to bring the phase change memory elements in the amorphous state;

apply as programming signals current pulses to the phase change memory elements that heat the phase change memory elements above the crystallization temperature, thereby lowering the conductance of the phase change memory elements to a desired conductance value.

10. A sensor device according to claim 1 , wherein the computational memory comprises a first memristive array for programming a measurement matrix and a second memristive array for programming a transpose of the measurement matrix.

11. A sensor device according to claim 1 , wherein the reconstruction algorithm is an approximate message passing algorithm.

12. A sensor device according to claim 1 , wherein the reconstruction algorithm comprises an integrated de-noising functionality.

13. A sensor device according to claim 1 , wherein the device is configured to perform a block-based compression and reconstruction.

14. A method for signal compression and reconstruction, the method comprising:

receiving, by a sensor device, an input signal, the sensor device comprising a computational memory and electronic circuitry, the computational memory comprising at least two programmable resistance states;

computing, by the computational memory, a compressed signal from the input signal;

performing, by the electronic circuitry, a reconstruction algorithm to compute a reconstructed signal from the compressed signal;

computing, by the computational memory, partial results of the reconstruction algorithm; and

providing, by the computational memory, the partial results to the electronic circuitry.

15. A method according to claim 14 , further comprising

applying programming signals to resistive memory elements of the computational memory to program conductance values as a measurement matrix;

compressing the input signal by performing a matrix-vector multiplication of the input signal with the measurement matrix; and

computing the partial results of the reconstruction algorithm by performing matrix-vector multiplications with the measurement matrix.

16. A method according to claim 14 , further comprising

applying read voltages to row lines and/or column lines of a memristive array of the computational memory;

reading out current values of the row lines and/or column lines of the memristive array; wherein

the read voltages represent vector values of a vector of a matrix-vector multiplication; and

the current values represent result values of vector elements of a product vector of the matrix-vector multiplication.

17. A method according to claim 14 , wherein the reconstruction algorithm is an approximate message passing algorithm.

18. A design structure tangibly embodied in a machine readable medium for designing, manufacturing, or testing an integrated circuit, the design structure comprising:

a sensor device comprising a computational memory, the computational memory comprising at least two programmable resistance states, and

electronic circuitry;

the sensor device being configured to

receive an input signal;

compress the input signal into a compressed signal; and

compute a reconstructed signal from the compressed signal;

wherein the electronic circuitry is configured to perform a reconstruction algorithm to compute the reconstructed signal; and

the computational memory is configured to compute the compressed signal and partial results of the reconstruction algorithm.

19. A design structure according to claim 18 , wherein the computational memory comprises at least one memristive array comprising a plurality of resistive memory elements, wherein the memristive array comprises a plurality of row lines and a plurality of columns lines, wherein the plurality of row lines extend in a first x-y-plane and the plurality of column lines extend in a second x-y plane, wherein the first x-y plane is arranged in a vertical z-direction with respect to the second x-y-plane.

20. A design structure according to claim 19 , wherein the memristive array further comprises

a plurality of junctions arranged between the plurality of row lines and the plurality of column lines, wherein each junction comprises a programmable resistive memory element.

Assignments (1)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Jun 4, 2019
From: LE GALLO-BOURDEAU, MANUEL; SEBASTIAN, ABU; CHERUBINI, GIOVANNI
To: INTERNATIONAL BUSINESS MACHINES CORPORATION
Reel/Frame 049360/0024 →
Continuity (3)
Continuation 16031041 · Jul 10, 2018
Provisional Application 62576084 · Oct 24, 2017
Related Publication 20190287613A1 · Sep 19, 2019
Cited By (1)
US 12,456,291