IP Library › Granted Patent US 10,861,701
Granted Patent B2
US 10,861,701 · App. 14/754,427 · Granted Dec 8, 2020

Semiconductor device and manufacturing method thereof

Inventors: Jia-Ming Lin (Tainan, TW); Shiu-Ko Jangjian (Tainan, TW); Chun-Che Lin (Tainan, TW)
Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
H01L21/28568H01L21/28088H01L21/76843H01L21/76879H01L29/4966H01L29/66545H01L29/513H01L29/517
View Patent ↗
Loading inventors, assignments & file history…
Monitor This Case
Get email alerts when status or documents change.
Order Certified Copies
Most orders are placed with the USPTO same day — all within 24 business hours.
Order via The Patent Place →
Pre-filled with this patent's details
Quick Facts
Patent No.
US 10,861,701
App. No.
14/754,427
Granted
Dec 8, 2020
Kind
B2
Abstract

A semiconductor device includes a substrate, at least one layer, a metal adhesive, and a metal structure. The layer is disposed on the substrate. The layer has an opening, and the opening has a bottom surface and at least one sidewall. The metal adhesive is disposed on the bottom surface of the opening while leaving at least a portion of the sidewall of the opening exposed. The metal structure is disposed in the opening and on the metal adhesive.

Claims (51)

1. A semiconductor device, comprising:

a substrate; and

an N-channel transistor comprising:

a spacer structure;

a high-K dielectric layer having a first portion extending along a top surface of the substrate and a second portion extending along an inner sidewall of the spacer structure;

a first blocking layer over the high-K dielectric layer;

a second blocking layer disposed between the high-K dielectric layer and the first blocking layer;

a cap layer disposed on and in direct contact with the high-K dielectric layer, wherein the second blocking layer is disposed on the cap layer;

a work function metal layer disposed between the first blocking layer and the second blocking layer, wherein the second blocking layer is on a sidewall of the work function metal layer;

a metal adhesive disposed on the first blocking layer, wherein the metal adhesive comprises boron; and

a metal structure having a bottom in contact with the metal adhesive and a sidewall in direct contact with the first blocking layer.

2. The semiconductor device of claim 1 , wherein the metal adhesive is made of boron (B), tungsten boron (WB x ), tungsten boron silicon (WSi x B), or combinations thereof.

3. The semiconductor device of claim 1 , further comprising:

an interfacial layer disposed between the metal adhesive and the substrate, wherein the high-K dielectric layer is disposed on the interfacial layer.

4. The semiconductor device of claim 1 , wherein a thickness of the metal adhesive is in a range from about 1 Angstrom to about 20 Angstrom.

5. A semiconductor device, comprising:

a substrate; and

an N-channel transistor comprising:

a metal gate stack on the substrate, wherein the metal gate stack comprises:

an interfacial layer on the substrate;

a high-K dielectric layer on the interfacial layer, wherein the interfacial layer is between the substrate and the high-K dielectric layer;

a cap layer over the high-K dielectric layer, the cap layer comprising silicon;

a metal adhesive comprising boron;

a metal structure in contact with the metal adhesive;

a first blocking layer over the high-K dielectric layer and the cap layer and in contact with the metal adhesive and a sidewall of the metal structure;

a second blocking layer between the high-K dielectric layer and the first blocking layer; and

a work function metal layer wrapping around the first blocking layer.

6. The semiconductor device of claim 5 , wherein the metal adhesive is made of alloy.

7. The semiconductor device of claim 5 , wherein the metal adhesive is made of boron (B), tungsten boron (WB x ), tungsten boron silicon (WSi x B), or combinations thereof.

8. The semiconductor device of claim 5 , wherein the work function metal layer is between the first blocking layer and the second blocking layer.

9. The semiconductor device of claim 5 , wherein the second blocking layer is on the cap layer.

10. The semiconductor device of claim 5 , further comprising a spacer structure on a sidewall of the high-K dielectric layer.

11. The semiconductor device of claim 5 , wherein the cap layer is in direct contact with the high-K dielectric layer.

12. The semiconductor device of claim 5 , wherein the second blocking layer is on a sidewall of the work function metal layer.

13. The semiconductor device of claim 5 , wherein the metal adhesive is between the first blocking layer and the metal structure.

14. The semiconductor device of claim 5 , wherein the cap layer is spaced apart from the metal adhesive.

15. The semiconductor device of claim 5 , wherein the cap layer is spaced apart from the first blocking layer.

16. A semiconductor device, comprising:

a substrate;

an N-channel transistor comprising:

a metal structure;

a metal adhesive between the metal structure and the substrate, wherein the metal adhesive is in contact with a bottom of the metal structure;

a first blocking layer having a first portion in contact with a bottom of the metal adhesive and at least one second portion in direct contact with a sidewall of the metal adhesive and a sidewall of the metal structure;

a work function metal layer wrapping around the first blocking layer;

a second blocking layer wrapping around the work function metal layer;

a cap layer wrapping around the second blocking layer; and

a high-K dielectric layer wrapping around the cap layer.

17. The semiconductor device of claim 16 , wherein the metal adhesive is between the first portion of the first blocking layer and the metal structure.

18. The semiconductor device of claim 16 , wherein the metal adhesive and the first blocking layer comprise different metals.

19. The semiconductor device of claim 16 , wherein a thickness of the metal adhesive is in a range from about 1 Angstrom to about 20 Angstrom.

20. The semiconductor device of claim 16 , wherein the high-K dielectric layer is spaced apart from the substrate.

Assignments (1)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Jun 30, 2015
From: LIN, JIA-MING; JANGJIAN, SHIU-KO; LIN, CHUN-CHE
To: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
Reel/Frame 035941/0751 →
Continuity (1)
Related Publication 20160380066A1 · Dec 29, 2016
Cited By (1)
US 12,707,697