Power savings in processors

1. A method comprising:

generating, via a processing system, gate-level activity information of a software-programmable processor design for all possible executions of a target application for any possible inputs to the target application to identify parts of the processor design that are not exercised by the target application; and

determining, via the processing system, peak power and energy of the processor design based on the gate-level activity information for executing the target application on the processor,

wherein the determined peak power for executing the target application on the processor is less than a rated peak power of the processor design.

2. The method of claim 1 , wherein generating the gate-level activity information comprises performing symbolic simulation to identify unexercisable gates of the processor design.

3. The method of claim 2 , wherein performing symbolic simulation comprises:

initializing a list of unexercisable gates as all gates of the processor design;

initializing all inputs of the processor design to Xs, where each X represents an unknown logic value;

simulating the target application on the processor design; and

removing each gate that toggles and each gate through which an X propagates during the simulation from the list of unexercisable gates.

4. The method of claim 1 , wherein determining peak power and energy comprises:

generating an execution tree based on the gate-level activity information;

concatenating execution paths in the execution tree into a single execution trace; and

determining the peak power based on the single execution trace.

5. A method comprising:

generating, via a processing system, gate-level activity information of a processor design for all possible executions of a target application for any possible inputs to the target application; and

determining, via the processing system, peak power and energy of the processor design based on the gate-level activity information for executing the target application on the processor,

wherein determining peak power and energy comprises:

generating an execution tree based on the gate-level activity information;

concatenating execution paths in the execution tree into a single execution trace; and

determining the peak power based on the single execution trace, and

wherein determining the peak power based on the single execution trace comprises:

generating an even cycles power trace;

generating an odd cycles power trace; and

generating a peak power trace by interleaving power values from the even cycles in the even power trace and the odd cycles in the odd power trace; and

determining the peak power based on a maximum per cycle power value in the peak power trace.

6. The method of claim 4 , wherein determining the peak power and energy comprises:

generating a peak power trace based on the peak power for each execution path in the execution tree; and

determining the peak energy based on the peak power trace.

7. The method of claim 1 , further comprising:

sizing an energy harvester or energy storage device for the processor based on the determined peak power and energy.

8. A method comprising:

generating, via a processing system, gate-level activity information of a software-programmable processor design for all possible executions of a target application for any possible inputs to the target application to identify parts of the processor design that are not exercised by the target application;

grouping, via the processing system, gates of the processor design into a plurality of module-oblivious power domains based on the gate-level activity information, each of the plurality of module-oblivious power domains comprising an arbitrary set of gates having correlated activity; and

modifying, via the processing system, the target application to direct each of the plurality of module-oblivious power domains when to turn off and on.

9. The method of claim 8 , wherein generating the gate-level activity information comprises performing symbolic simulation to identify unexercisable gates of the processor design.

10. The method of claim 9 , wherein performing symbolic simulation comprises:

initializing a list of unexercisable gates as all gates of the processor design;

initializing all inputs of the processor design to Xs, where each X represents an unknown logic value;

simulating the target application on the processor design; and

removing each gate that toggles and each gate through which an X propagates during the simulation from the list of unexercisable gates.

11. The method of claim 8 , further comprising:

receiving gate-to-domain mapping information;

for each cycle of an execution path, determining the domains that have active gates based on the gate-level activity information and gate-to-domain mapping information;

marking a domain as active for an execution path in response to having active gates; and

annotating each instruction of the target application to specify which domains are used when the instruction is executed.

12. The method of claim 11 , further comprising:

receiving domain wakeup latencies,

wherein marking a domain as active comprises marking a domain as active during N cycles leading up to a period of activity, where N is the wakeup latency to power up the domain.

13. The method of claim 8 , further comprising:

sizing an energy harvester or energy storage device for the processor based on the module-oblivious power domains.