Synthesis path for transforming concurrent programs into hardware deployable on FPGA-based cloud infrastructures

1. An apparatus configured to create synchronous hardware accelerators from concurrent asynchronous programs, the apparatus comprising:

a processor configured to

obtain input as software instructions that describes concurrent behavior via a model of communicating sequential processes (CSP) of message exchange between concurrent processes performed via channels;

map each of the concurrent processes to synchronous dataflow primitives, comprising at least one of join, fork, merge, steer, variable, and arbiter;

produce a clocked digital logic description for upload to one or more field programmable gate array (FPGA) devices;

perform a primitive remap of the output design for throughput, clock rate and resource usage via a retime; and

create an annotated graph of the input software description for a debug of concurrent code for the field FPGA devices;

identify a main function;

parse a plurality of functions from the main function;

create a modified main function by a removal of the plurality of functions from the main function;

create the synchronous hardware accelerators based on the plurality of functions and store the synchronous hardware accelerators on a field programmable gate array (FPGA) memory space of the FPGA;

execute the modified main function;

call the synchronous hardware accelerators on the FPGA memory space based on the executed modified main function; and

provide a result of the modified main function execution to the computing device.

2. The apparatus of claim 1 , wherein the processor is further configured to store a replacement bit in memory to represent the main function, wherein the replacement bit is used as a signal to begin to process the main function.

3. The apparatus of claim 1 , wherein the synchronous hardware accelerators are accessed during an execution of the modified main function via channels.

4. The apparatus of claim 1 , wherein the parse of the plurality of functions from the main function further comprises an identification of instances of functions, identified by function syntax, and a removal of code associated with the plurality of functions from the modified main function.

5. The apparatus of claim 4 , wherein the processor is further configured to

create a different one of the synchronous hardware accelerators that correspond to each of the identified functions.

6. The apparatus of claim 5 , wherein the processor is further configured to

call at least one of the synchronous hardware accelerators from at least one other of the synchronous hardware accelerators from at least one of the channels that correspond to a specific memory location in the FPGA memory space.

7. The apparatus of claim 1 , wherein the main function is processed via a processor outside the FPGA, and wherein the modified main function being created further comprises a creation of references to each of the parsed functions and at least one reference to memory space locations, associated with the synchronous hardware accelerators, in the modified main function.

8. A method of creating synchronous hardware accelerators from concurrent asynchronous programs, the method comprising:

obtaining input as software instructions describing concurrent behavior via a model of communicating sequential processes (CSP) of message exchange between concurrent processes performed via channels;

mapping, on a computing device, each of the concurrent processes to synchronous dataflow primitives, comprising at least one of join, fork, merge, steer, variable, and arbiter;

producing a clocked digital logic description for upload to one or more field programmable gate array (FPGA) devices;

performing primitive remapping of the output design for throughput, clock rate and resource usage via retiming;

creating an annotated graph of the input software description for debugging of concurrent code for the field FPGA devices;

identifying a main function;

parsing a plurality of functions from the main function;

creating a modified main function by removing the plurality of functions from the main function;

creating the synchronous hardware accelerators based on the plurality of functions and storing the synchronous hardware accelerators on a field programmable gate array (FPGA) memory space of the FPGA;

executing the modified main function;

calling the synchronous hardware accelerators on the FPGA memory space based on the executed modified main function; and

providing a result of the modified main function execution to the computing device.

9. The method of claim 8 , further comprising:

storing a replacement bit in memory to represent the main function, wherein the replacement bit is used as a signal to begin processing the main function.

10. The method of claim 8 , wherein the synchronous hardware accelerators are accessed during executing of the modified main function via the channels.

11. The method of claim 8 , wherein the parsing of the plurality of functions from the main function further comprises identifying instances of functions, identified by function syntax, and removing code associated with the plurality of functions from the modified main function.

12. The method of claim 11 , further comprising:

creating a different one of the synchronous hardware accelerators corresponding to each of the identified functions.

13. The method of claim 12 , further comprising:

calling at least one of the synchronous hardware accelerators from at least one other of the synchronous hardware accelerators from at least one of the channels corresponding to a specific memory location in the FPGA memory space.

14. The method of claim 8 , wherein the main function is processed via a processor outside the FPGA, and wherein creating the modified main function further comprises creating references to each of the parsed functions and at least one reference to memory space locations, associated with the synchronous hardware accelerators, in the modified main function.

15. A non-transitory computer readable storage medium configured to store instructions that when executed causes a processor to perform creating synchronous hardware accelerators from concurrent asynchronous programs, the processor being configured to perform:

obtaining input as software instructions describing concurrent behavior via a model of communicating sequential processes (CSP) of message exchange between concurrent processes performed via channels;

mapping, on a computing device, each of the concurrent processes to synchronous dataflow primitives, comprising at least one of join, fork, merge, steer, variable, and arbiter;

producing a clocked digital logic description for upload to one or more field programmable gate array (FPGA) devices;

performing primitive remapping of the output design for throughput, clock rate and resource usage via retiming;

creating an annotated graph of the input software description for debugging of concurrent code for the field FPGA devices;

identifying a main function;

parsing a plurality of functions from the main function;

creating a modified main function by removing the plurality of functions from the main function;

creating the synchronous hardware accelerators based on the plurality of functions and storing the synchronous hardware accelerators on a field programmable gate array (FPGA) memory space of the FPGA;

executing the modified main function;

calling the synchronous hardware accelerators on the FPGA memory space based on the executed modified main function; and

providing a result of the modified main function execution to the computing device.

16. The non-transitory computer readable storage medium of claim 15 , wherein the processor is further configured to perform:

storing a replacement bit in memory to represent the main function, wherein the replacement bit is used as a signal to begin processing the main function.

17. The non-transitory computer readable storage medium of claim 15 , wherein the synchronous hardware accelerators are accessed during executing of the modified main function via the channels.

18. The non-transitory computer readable storage medium of claim 15 , wherein the parsing of the plurality of functions from the main function further comprises identifying instances of functions, identified by function syntax, and removing code associated with the plurality of functions from the modified main function.

19. The non-transitory computer readable storage medium of claim 18 , wherein the processor is further configured to perform:

creating a different one of the synchronous hardware accelerators corresponding to each of the identified functions.

20. The non-transitory computer readable storage medium of claim 18 , wherein the processor is further configured to perform:

calling at least one of the synchronous hardware accelerators from at least one other of the synchronous hardware accelerators from at least one of the channels corresponding to a specific memory location in the FPGA memory space, and wherein the main function is processed via a processor outside the FPGA, and wherein creating the modified main function further comprises creating references to each of the parsed functions and at least one reference to memory space locations, associated with the synchronous hardware accelerators, in the modified main function.