Programmatically generating software test libraries for functional safety

1. A computing system comprising:

a network controller;

a processor coupled to the network controller; and

a memory coupled to the processor, the memory including instructions, which when executed by the processor, cause the computing system to:

apply a functional safety test stimulus to a hardware level simulator, the hardware level simulator to simulate a hardware system,

compile an output of the hardware level simulator into a software test library (STL) file, and

verify that a diagnostic coverage of the STL file approximates a diagnostic coverage of the functional safety test stimulus,

wherein the output of the hardware level simulator is to include an instruction stream file, and wherein to compile the output of the hardware level simulator, the instructions, when executed, cause the computing system to:

extract an opcode stream from the instruction stream file,

translate the opcode stream into assembly code, and

generate one or more flow graphs based on the assembly code, wherein the one or more flow graphs reconstruct functional blocks of sequential code in the functional safety test stimulus,

wherein the output of the hardware level simulator is to further include a memory trace file, and wherein to compile the output of the hardware level simulator, the instructions, when executed, further cause the computing system to generate the STL file based on the one or more flow graphs and the memory trace file.

2. The computing system of claim 1 , wherein to extract the opcode stream from the instruction stream file, the instructions, when executed, cause the computing system to generate an abstract syntax tree based on the instruction stream file.

3. The computing system of claim 1 , wherein the output of the hardware level simulator is to include an enhanced value change dump file and a coverage file that indicates the diagnostic coverage of the functional safety test stimulus, and wherein to verify the diagnostic coverage of the STL file, the instructions, when executed, cause the computing system to:

apply the extended value change dump file and the STL file to a fault simulator, wherein an output of the fault simulator indicates the diagnostic coverage of the STL file, and compare the output of the fault simulator to the coverage file.

4. The computing system of claim 3 , wherein the instructions, when executed, cause the computing system to re-compile the output of the hardware level simulator with an adjusted cost function if the diagnostic coverage of the STL file does not approximate the diagnostic coverage of the functional safety test stimulus.

5. A semiconductor apparatus comprising:

one or more substrates; and

logic coupled to the one or more substrates, wherein the logic is implemented at least partly in one or more of configurable logic or fixed-functionality hardware logic, the logic coupled to the one or more substrates to:

apply a functional safety test stimulus to a hardware level simulator, the hardware level simulator to simulate a hardware system,

compile an output of the hardware level simulator into a software test library (STL) file, and

verify that a diagnostic coverage of the STL file approximates a diagnostic coverage of the functional safety test stimulus,

wherein the output of the hardware level simulator is to include an instruction stream file, and wherein to compile the output of the hardware level simulator, the logic is to:

extract an opcode stream from the instruction stream file,

translate the opcode stream into assembly code, and

generate one or more flow graphs based on the assembly code, wherein the one or more flow graphs reconstruct functional blocks of sequential code in the functional safety test stimulus,

wherein the output of the hardware level simulator is to further include a memory trace file, and wherein to compile the output of the hardware level simulator, the logic is to generate the STL file based on the one or more flow graphs and the memory trace file.

6. The semiconductor apparatus of claim 5 , wherein to extract the opcode stream from the instruction stream file, the instructions, when executed, cause the computing system to generate an abstract syntax tree based on the instruction stream file.

7. The semiconductor apparatus of claim 5 , wherein the output of the hardware level simulator is to include an enhanced value change dump file and a coverage file that indicates the diagnostic coverage of the functional safety test stimulus, and wherein to verify the diagnostic coverage of the STL file, the logic is to:

apply the extended value change dump file and the STL file to a fault simulator, wherein an output of the fault simulator indicates the diagnostic coverage of the STL file, and

compare the output of the fault simulator to the coverage file.

8. The semiconductor apparatus of claim 7 , wherein the logic is to re-compile the output of the hardware level simulator with an adjusted cost function if the diagnostic coverage of the STL file does not approximate the diagnostic coverage of the functional safety test stimulus.

9. At least one computer readable storage medium comprising a set of instructions, which when executed by a computing system, cause the computing system to:

apply a functional safety test stimulus to a hardware level simulator, the hardware level simulator to simulate a hardware system;

compile an output of the hardware level stimulator into a software test library (STL) file; and

verify that a diagnostic coverage of the STL file approximates a diagnostic coverage of the functional safety test stimulus,

wherein the output of the hardware level simulator is to include an instruction stream file, and wherein to compile the output of the hardware level simulator, the instructions, when executed, cause the computing system to:

extract an opcode stream from the instruction stream file;

translate the opcode stream into assembly code; and

generate one or more flow graphs based on the assembly code, wherein the one or more flow graphs reconstruct functional blocks of sequential code in the functional safety test stimulus,

wherein the output of the hardware level simulator is to further include a memory trace file, and wherein to compile the output of the hardware level simulator, the instructions, when executed, further cause the computing system to generate the STL file based on the one or more flow graphs and the memory trace file.

10. The at least one computer readable storage medium of claim 9 , wherein to extract the opcode stream from the instruction stream file, the instructions, when executed, cause the computing system to generate an abstract syntax tree based on the instruction stream file.

11. The at least one computer readable storage medium of claim 9 , wherein the output of the hardware level simulator is to include an enhanced value change dump file and a coverage file that indicates the diagnostic coverage of the functional safety test stimulus, and wherein to verify the diagnostic coverage of the STL file, the instructions, when executed, cause the computing system to:

apply the extended value change dump file and the STL file to a fault simulator, wherein an output of the fault simulator indicates the diagnostic coverage of the STL file; and

compare the output of the fault simulator to the coverage file.

12. The at least one computer readable storage medium of claim 11 , wherein the instructions, when executed, cause the computing system to re-compile the output of the hardware level simulator with an adjusted cost function if the diagnostic coverage of the STL file does not approximate the diagnostic coverage of the functional safety test stimulus.

13. A method comprising:

applying a functional safety test stimulus to a hardware level simulator, wherein the hardware level simulator simulates a hardware system;

compiling an output of the hardware level simulator into a software test library (STL) file; and

verifying that a diagnostic coverage of the STL file approximates a diagnostic coverage of the functional safety test stimulus,

wherein the output of the hardware level simulator includes an instruction stream file, and wherein compiling the output of the hardware level simulator includes:

extracting an opcode stream from the instruction stream file;

translating the opcode stream into assembly code; and

generating one or more flow graphs based on the assembly code, wherein the one or more flow graphs reconstruct functional blocks of sequential code in the functional safety test stimulus,

wherein the output of the hardware level simulator further includes a memory trace file, and wherein compiling the output of the hardware level simulator further includes generating the STL file based on the one or more flow graphs and the memory trace file.

14. The method of claim 13 , wherein extracting the opcode stream from the instruction stream file includes generating an abstract syntax tree based on the instruction stream file.

15. The method of claim 13 , wherein the output of the hardware level simulator includes an enhanced value change dump file and a coverage file that indicates the diagnostic coverage of the functional safety test stimulus, and wherein verifying the diagnostic coverage of the STL file includes:

applying the extended value change dump file and the STL file to a fault simulator, wherein an output of the fault simulator indicates the diagnostic coverage of the STL file; and

comparing the output of the fault simulator to the coverage file.

16. The method of claim 15 , further including re-compiling the output of the hardware level simulator with an adjusted cost function if the diagnostic coverage of the STL file does not approximate the diagnostic coverage of the functional safety test stimulus.