Semiconductor device and method
In an embodiment, a method includes: forming a gate dielectric layer on an interface layer; forming a doping layer on the gate dielectric layer, the doping layer including a dipole-inducing element; annealing the doping layer to drive the dipole-inducing element through the gate dielectric layer to a first side of the gate dielectric layer adjacent the interface layer; removing the doping layer; forming a sacrificial layer on the gate dielectric layer, a material of the sacrificial layer reacting with residual dipole-inducing elements at a second side of the gate dielectric layer adjacent the sacrificial layer; removing the sacrificial layer; forming a capping layer on the gate dielectric layer; and forming a gate electrode layer on the capping layer.
1. A device comprising:
a first interface layer on a substrate, a first portion of the first interface layer being doped with a dipole-inducing element;
a first gate dielectric layer on the first interface layer, a second portion of the first gate dielectric layer being doped with the dipole-inducing element, a first interface of the first gate dielectric layer and the first interface layer having a first concentration of the dipole-inducing element;
a first capping layer on the first gate dielectric layer, a second interface of the first capping layer and the first gate dielectric layer being free from the dipole-inducing element; and
a first gate electrode on the first capping layer.
2. The device of claim 1 , wherein a third interface of the first interface layer and the substrate is free from the dipole-inducing element.
3. The device of claim 1 , wherein a second concentration of the dipole-inducing element in the first interface layer increases in a first direction extending from the substrate towards the first gate electrode.
4. The device of claim 3 , wherein a third concentration of the dipole-inducing element in the first gate dielectric layer decreases in the first direction.
5. The device of claim 1 , wherein the dipole-inducing element is La.
6. The device of claim 1 , wherein the first capping layer comprises TiSiN.
7. The device of claim 1 further comprising:
a second interface layer on the substrate, a third portion of the second interface layer being doped with the dipole-inducing element;
a second gate dielectric layer on the second interface layer, a fourth portion of the second gate dielectric layer being doped with the dipole-inducing element, a third interface of the second gate dielectric layer and the second interface layer having a second concentration of the dipole-inducing element, the second concentration being different from the first concentration;
a second capping layer on the second gate dielectric layer, a fourth interface of the second capping layer and the second gate dielectric layer being free from the dipole-inducing element; and
a second gate electrode on the second capping layer.
8. The device of claim 7 , wherein a third concentration of the dipole-inducing element in the first interface layer increases in a first direction extending from the substrate towards the first gate electrode, and a fourth concentration of the dipole-inducing element in the second interface layer increases in a second direction extending from the substrate towards the second gate electrode, a rate of increase of the fourth concentration being different than a rate of increase of the third concentration.
9. The device of claim 8 , wherein a fifth concentration of the dipole-inducing element in the first gate dielectric layer decreases in the first direction, and a sixth concentration of the dipole-inducing element in the second gate dielectric layer decreases in the second direction, a rate of decrease of the sixth concentration being different than a rate of decrease of the fifth concentration.
10. The device of claim 7 , wherein the substrate comprises a first fin and a second fin, the first interface layer disposed on the first fin, the second interface layer disposed on the second fin.
11. The device of claim 7 , wherein the substrate comprises a fin, the first interface layer disposed on the fin, the second interface layer disposed on the fin.
12. A device comprising:
a substrate;
a first transistor comprising:
a first interface layer on the substrate;
a first gate dielectric layer on the first interface layer, an interface of the first gate dielectric layer and the first interface layer having a first concentration of a dipole-inducing element;
a first capping layer on the first gate dielectric layer, an interface of the first capping layer and the first gate dielectric layer having a second concentration of the dipole-inducing element, the second concentration being less than the first concentration; and
a first gate electrode on the first capping layer; and
a second transistor comprising:
a second interface layer on the substrate;
a second gate dielectric layer on the second interface layer, an interface of the second gate dielectric layer and the second interface layer having a third concentration of the dipole-inducing element;
a second capping layer on the second gate dielectric layer, an interface of the second capping layer and the second gate dielectric layer having a fourth concentration of the dipole-inducing element, the fourth concentration being less than the third concentration, the fourth concentration being different from the second concentration; and
a second gate electrode on the second capping layer.
13. The device of claim 12 , wherein the dipole-inducing element is La.
14. The device of claim 12 , wherein the first capping layer and the second capping layer each comprise TiSiN.
15. The device of claim 12 , wherein the substrate comprises a first fin and a second fin, the first interface layer disposed on the first fin, the second interface layer disposed on the second fin.
16. The device of claim 12 , wherein the substrate comprises a fin, the first interface layer disposed on the fin, the second interface layer disposed on the fin.
17. The device of claim 12 , wherein the second concentration and the fourth concentration are non-zero.
18. The device of claim 12 , wherein the second concentration and the fourth concentration are zero.
19. A method comprising:
depositing an interface layer on a substrate;
depositing a gate dielectric layer on the interface layer;
forming a first doping layer on a first portion of the gate dielectric layer, the first doping layer comprising a dipole-inducing element;
annealing the first doping layer to drive the dipole-inducing element through the first portion of the gate dielectric layer to a first interface of the gate dielectric layer and the interface layer;
forming a second doping layer on a second portion of the gate dielectric layer, the second doping layer comprising the dipole-inducing element, a first thickness of the first doping layer being different than a second thickness of the second doping layer;
annealing the second doping layer to drive the dipole-inducing element through the second portion of the gate dielectric layer to the first interface of the gate dielectric layer and the interface layer;
forming a sacrificial layer on the gate dielectric layer, a material of the sacrificial layer reacting with residual dipole-inducing elements at a second interface of the sacrificial layer and the gate dielectric layer;
removing the sacrificial layer;
forming a capping layer on the gate dielectric layer; and
forming a gate electrode layer on the capping layer.
20. The method of claim 19 , wherein the sacrificial layer and the capping layer are formed of the same material.