IP Library › Granted Patent US 10,868,122
Granted Patent B2
US 10,868,122 · App. 16/427,844 · Granted Dec 15, 2020

Silicon carbide semiconductor device and a method of manufacturing the silicon carbide semiconductor device

Inventors: Takeshi Tawara (Tsukuba, JP); Koji Nakayama (Tsukuba, JP); Yoshiyuki Yonezawa (Tsukuba, JP); Hidekazu Tsuchida (Yokosuka, JP); Koichi Murata (Yokosuka, JP)
Assignee: FUJI ELECTRIC CO., LTD.
H01L29/1608H01L29/6606H01L29/868
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Quick Facts
Patent No.
US 10,868,122
App. No.
16/427,844
Granted
Dec 15, 2020
Kind
B2
Abstract

During epitaxial growth of an n − -type drift layer having a uniform nitrogen concentration, vanadium is doped in addition to the nitrogen, whereby an n − -type lifetime reduced layer is selectively formed in the n − -type drift layer. The n − -type lifetime reduced layer is disposed at a depth that is more than 5 μm from a pn junction surface between a p-type anode layer and the n − -type drift layer in a direction toward a cathode side, and the n − -type lifetime reduced layer is disposed separated from the pn junction surface. Further, the n − -type lifetime reduced layer is disposed in a range from the pn junction surface to a depth that is ⅓ times a thickness of the n − -type drift layer. A vanadium concentration of the n − -type lifetime reduced layer is 1/100 to ⅕ of a nitrogen concentration of the n − -type lifetime reduced layer.

Claims (12)

1. A silicon carbide semiconductor device having a pn junction surface through which forward current flows, the silicon carbide semiconductor device comprising:

a starting substrate;

a first-conductivity-type epitaxial layer that is made of silicon carbide containing, as an impurity, a first element that is a dopant of a first conductivity type, and that includes, in the order recited, a first first-conductivity-type epitaxial layer disposed proximate to the starting substrate; a second first-conductivity-type epitaxial layer disposed on the first first-conductivity-type epitaxial layer; and a third first-conductivity-type epitaxial layer disposed on the second first-conductivity-type epitaxial layer; and

a second-conductivity-type epitaxial layer that is made of silicon carbide containing a dopant of a second conductivity type and that has the pn junction surface provided between the second-conductivity-type epitaxial layer and the first-conductivity-type epitaxial layer so that minority carriers are supplied to the first-conductivity-type epitaxial layer,

wherein the second first-conductivity-type epitaxial layer contains, as impurities, the first element and a second element, vanadium, that forms a recombination center therein, and is positioned at a first depth that is separated from and deeper than 5 μm from the pn junction surface in a direction toward the first first-conductivity-type epitaxial layer, and is disposed in a range from the pn junction surface to a second depth that is ⅓ times a thickness of the first-conductivity-type epitaxial layer,

wherein the third first-conductivity-type epitaxial layer contains more of the first element than does the second first-conductivity-type epitaxial layer due to a depth distribution of a first-conductivity-type doping concentration of the first-conductivity-type epitaxial layer; and

wherein the second element of the second first-conductivity-type epitaxial layer has a concentration that ranges from 1/100 to ⅕ of the concentration of the first element of the second first-conductivity-type epitaxial layer.

2. The silicon carbide semiconductor device according to claim 1 , wherein the third first-conductivity-type epitaxial layer does not contain the second element and has a carrier lifetime that is at least 10 μs.

3. The silicon carbide semiconductor device according to claim 1 , wherein the silicon carbide semiconductor device is any one of a PiN diode, a metal oxide semiconductor field effect transistor (MOSFET), an insulated gate bipolar transistor (IGBT), and a gate turn-off (GTO) thyristor.

4. A method of manufacturing the silicon carbide semiconductor device according to claim 1 , the method comprising:

applying a predetermined voltage between both surfaces of the first-conductivity-type epitaxial layer effective to cause a depletion layer in the first-conductivity-type epitaxial layer to spread; and

obtaining a depth distribution of a first-conductivity-type doping concentration of the first-conductivity-type epitaxial layer, based on an amount of change in capacitance of the depletion layer.

Assignments (1)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded May 31, 2019
From: TAWARA, TAKESHI; NAKAYAMA, KOJI; YONEZAWA, YOSHIYUKI; TSUCHIDA, HIDEKAZU; MURATA, KOICHI
To: FUJI ELECTRIC CO., LTD.
Reel/Frame 049330/0301 →
Priority Claims (1)
JP 2018-120289 · Jun 25, 2018 · national
Continuity (1)
Related Publication 20190393312A1 · Dec 26, 2019