IP Library Granted Patent US 10,872,941
Granted Patent B2
US 10,872,941 · App. 16/518,246 · Granted Dec 22, 2020

Display panel, manufacture method thereof and display device

Inventors: Pinfan Wang (Beijing, CN); Pohsien Wu (Beijing, CN); Mingche Hsieh (Beijing, CN)
Assignee: BOE TECHNOLOGY GROUP CO., LTD.
H01L27/3246G03F7/094
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Quick Facts
Patent No.
US 10,872,941
App. No.
16/518,246
Granted
Dec 22, 2020
Kind
B2
Abstract

A display panel is provided, which includes a substrate, multiple light emitting structures arranged in an array on the substrate, a blocking structure at least arranged in a peripheral region of the substrate, and a cathode layer arranged on the multiple light emitting structures and the blocking structure. The cathode layer is discontinuous at a location corresponding to the blocking structure.

Claims (47)

1. A display panel, comprising:

a substrate;

a plurality of light emitting structures arranged in an array on the substrate;

a blocking structure, at least arranged in a peripheral region of the substrate; and

a cathode layer, arranged on the plurality of light emitting structures and the blocking structure,

wherein the cathode layer is discontinuous at a location corresponding to the blocking structure, and

wherein a material of the blocking structure comprises photoresist.

2. The display panel according to claim 1 , wherein the blocking structure comprises a first blocking structure arranged in peripheral regions of at least a part of the plurality of light emitting structures.

3. The display panel according to claim 1 , wherein an orthographic projection area of a top surface of the blocking structure onto the substrate is larger than an orthographic projection area of a bottom surface of the blocking structure onto the substrate.

4. The display panel according to claim 3 , wherein a cross-sectional shape of the blocking structure is an inverted trapezoid or a columnar structure having a mushroom head.

5. The display panel according to claim 3 , wherein there is a gap between the cathode layer and a side wall of the blocking structure.

6. The display panel according to claim 1 , further comprising a pixel defining layer arranged in peripheral regions of the plurality of light emitting structures,

wherein the blocking structure is arranged on the pixel defining layer.

7. The display panel according to claim 1 , further comprising a planarization layer and a pixel defining layer,

wherein the planarization layer is arranged between the substrate and the light emitting structures,

the pixel defining layer is arranged on the planarization layer and in peripheral regions of the plurality of light emitting structures, and

the blocking structure is arranged on the planarization layer.

8. The display panel according to claim 1 , wherein an opening is provided in a peripheral region of each of at least a part of the plurality of light emitting structures, and

the blocking structure comprises a second blocking structure around the opening.

9. The display panel according to claim 1 , further comprising a packaging layer arranged on the cathode layer and covering the substrate.

10. A display device, comprising the display panel according to claim 1 .

11. A display panel, comprising:

a substrate;

a plurality of light emitting structures arranged in an array on the substrate;

a blocking structure, at least arranged in a peripheral region of the substrate; and

a cathode layer, arranged on the plurality of light emitting structures and the blocking structure,

wherein an orthographic projection area of a top surface of the blocking structure onto the substrate is larger than an orthographic projection area of a bottom surface of the blocking structure onto the substrate, and

wherein the cathode layer is in contact with a side wall of the blocking structure.

12. A method for manufacturing a display panel, comprising:

forming a plurality of light emitting structures in an array on a substrate;

forming a blocking structure, wherein the blocking structure is at least arranged in a peripheral region of the substrate; and

forming a cathode layer on the plurality of light emitting structures and the blocking structure,

wherein the cathode layer is discontinuous at a location corresponding to the blocking structure, and

wherein a material of the blocking structure comprises photoresist.

13. The method according to claim 12 , wherein the blocking structure comprises a first blocking structure arranged in peripheral regions of at least a part of the plurality of light emitting structures.

14. The method according to claim 12 , wherein an orthographic projection area of a top surface of the blocking structure onto the substrate is larger than an orthographic projection area of a bottom surface of the blocking structure onto the substrate.

15. The method according to claim 14 , wherein a cross-sectional shape of the blocking structure is an inverted trapezoid or a columnar structure having a mushroom head.

16. The method according to claim 14 , wherein the cathode layer is in contact with a side wall of the blocking structure or there is a gap between the cathode layer and the side wall of the blocking structure.

17. The method according to claim 12 , further comprising forming a pixel defining layer,

wherein the pixel defining layer is arranged in peripheral regions of the plurality of light emitting structures, and

the blocking structure is arranged on the pixel defining layer.

18. The method according to claim 12 , further comprising forming a planarization layer and a pixel defining layer,

wherein the planarization layer is arranged between the substrate and the light emitting structures,

the pixel defining layer is arranged on the planarization layer and in peripheral regions of the plurality of light emitting structures, and

the blocking structure is arranged on the planarization layer.

19. The method according to claim 12 , wherein an opening is provided in a peripheral region of each of at least a part of the plurality of light emitting structures, and

the blocking structure comprises a second blocking structure around the opening.

Assignments (2)
CORRECTIVE ASSIGNMENT TO CORRECT THE ORDER OF THE ASSIGNEES TO READ -- PINFAN WANG; POHSIEN WU; MINGCHE HSIEH -- PREVIOUSLY RECORDED ON REEL 049835 FRAME 0004. ASSIGNOR(S) HEREBY CONFIRMS THE ASSIGNMENT. Recorded Nov 18, 2020
From: WANG, PINFAN; WU, POHSIEN; HSIEH, MINGCHE
To: BOE TECHNOLOGY GROUP CO., LTD.
Reel/Frame 054475/0412 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Jul 23, 2019
From: WANG, PINFAN; HSIEH, MINGCHE; WU, POHSIEN
To: BOE TECHNOLOGY GROUP CO., LTD.
Reel/Frame 049835/0004 →
Priority Claims (1)
CN 2018 1 0805652 · Jul 20, 2018 · national
Continuity (1)
Related Publication 20200027936A1 · Jan 23, 2020