Detecting silent data corruption for mass storage devices

1. A storage controller, comprising:

host data segmentation circuitry to divide a data payload into a plurality of data segments, in response to a write command from a host domain to write the data payload to a storage device;

cyclic redundancy check (CRC) encode circuitry to generate a plurality of CRC codes, each of the plurality of CRC codes originally paired with a corresponding one of the plurality of data segments;

CRC reordering encode circuitry to shift each of the plurality of CRC codes to pair with a new data segment different from an originally paired data segment, including any of a subsequent data segment, previous data segment, and random data segment relative to the originally paired data segment; and

wherein, based on one or more shifted CRC codes, CRC decode circuitry will produce a CRC failure of all of the plurality of data segments, including data segments that were successfully written, if any of the plurality of data segments of the data payload were not successfully written before a system interruption event occurred.

2. The storage controller of claim 1 , further comprising segment sectorization circuitry to divide each of the plurality of data segments into a plurality of sector-length portions; wherein each sector-length portion having a bit length based on a sector size of the storage device.

3. The storage controller of claim 2 , further comprising error correction code (ECC) encode circuitry to generate ECC code for each sector-length portion.

4. The storage controller of claim 2 , wherein the host data segmentation circuitry to divide the data payload by 2 N ; and wherein the segment sectorization circuitry to divide each data segment by 2 (N+X) ; where N and X are whole numbers.

5. The storage controller of claim 3 , wherein the segment sectorization circuitry further to, except for the last sector-length portion of a data segment, generate a null field for each sector-length portion and assemble the null field and the ECC code for each sector-length portion; and further to, for the last sector-length portion of the segment, assemble the ECC code and a CRC code from the originally paired data segment.

6. The storage controller of claim 3 , further comprising:

CRC reordering decode circuitry to, in response to a data read command from the host domain to read the data payload from the storage device, reassign a shifted CRC code to the originally paired data segment;

CRC decode circuitry to decode a reassigned CRC code for each data segment to determine a first data integrity status; and

ECC decode circuitry to decode the ECC code of each sector-length portion to determine a second data integrity status.

7. The storage controller of claim 1 , further comprising:

CRC reordering decode circuitry to, in response to a data read command from the host domain to read the data payload from the storage device, reassign a shifted CRC code to the originally paired data segment; and

CRC decode circuitry to decode a reassigned CRC code for each data segment to determine a data integrity status.

8. The storage controller of claim 1 , wherein the host data segmentation circuitry to divide the data payload by 2 N ; where N is a whole number.

9. A method comprising:

dividing, by host data segmentation circuitry, in response to a write command from a host domain to write a data payload to a storage device, the data payload into a plurality of data segments;

generating, by cyclic redundancy check (CRC) encode circuitry, a plurality of cyclic redundancy check (CRC) codes, each of the plurality of CRC codes originally paired with a corresponding one of the plurality of data segments; and

shifting, by CRC reordering encode circuitry, each of the plurality of CRC codes to pair with a new data segment different from an originally paired data segment, including any of a subsequent data segment, previous data segment, and random data segment relative to the originally paired data segment; and

producing based on one or more shifted CRC codes, by CRC decode circuitry, a CRC failure of all of the plurality of data segments, including data segments that were successfully written, if any of the plurality of data segments of the data payload were not successfully written before a system interruption event occurred.

10. The method of claim 9 , further comprising:

dividing each of the plurality of data segments into a plurality of sector-length portions;

wherein each sector-length portion having a bit length based on a sector size of the storage device.

11. The method of claim 10 , comprising dividing the data payload by 2 N ; and dividing each data segment by 2 (N+X) ; where N and X are whole numbers.

12. The method of claim 10 , further comprising generating error correction code (ECC) code for each sector-length portion.

13. The method of claim 12 , further comprising:

generating, except for the last sector-length portion of a data segment, a null field for each sector-length portion and assembling the null field and the ECC code for each sector-length portion; and

assembling, for the last sector-length portion of the data segment, the ECC code and a CRC code from the originally paired data segment.

14. The method of claim 13 , further comprising:

reassigning, in response to a data read command from the host domain to read the data payload from the storage device, a shifted CRC code to the originally paired data segment; and

decoding a reassigned CRC code for each data segment to determine a first data integrity status; and

decoding the ECC code of each sector-length portion to determine a second data integrity status.

15. The method of claim 9 , further comprising:

reassigning, in response to a data read command from the host domain to read the data payload from the storage device, a shifted CRC code to the originally paired data segment; and

decoding a reassigned CRC code for each data segment to determine a data integrity status.

16. The method of claim 9 , comprising dividing the data payload by 2 N ; where N is a whole number.

17. A storage system, comprising:

a storage device having a plurality of sectors; and;

a storage controller comprising:

host data segmentation circuitry to divide a data payload into a plurality of data segments, in response to a write command from a host domain to write the data payload to the storage device;

cyclic redundancy check (CRC) encode circuitry to generate a plurality of CRC codes, each of the plurality of CRC codes originally paired with a corresponding one of the plurality of data segments;

CRC reordering encode circuitry to shift each of the plurality of CRC codes to pair with a new data segment different from an originally paired data segment, including any of a subsequent data segment, previous data segment, and random data segment relative to the originally paired data segment; and

wherein, based on one or more shifted CRC codes, CRC decode circuitry will produce a CRC failure of all of the plurality of data segments, including data segments that were successfully written, if any of the plurality of data segments of the data payload were not successfully written before a system interruption event occurred.

18. The storage system of claim 17 , further comprising segment sectorization circuitry to divide each of the plurality of data segments into a plurality of sector-length portions; wherein each sector-length portion having a bit length based on a sector size of the storage device.

19. The storage system of claim 18 , further comprising error correction code (ECC) encode circuitry to generate ECC code for each sector-length portion.

20. The storage system of claim 19 , wherein the segment sectorization circuitry further to, except for the last sector-length portion of a data segment, generate a null field for each sector-length portion and assemble the null field and the ECC code for each sector-length portion; and further to, for the last sector-length portion of the data segment, assemble the ECC code and a CRC code from the originally paired data segment.

21. The storage system of claim 18 , wherein the host data segmentation circuitry to divide the data payload by 2 N ; and wherein the segment sectorization circuitry to divide each data segment by 2 (N+X) ; where N and X are whole numbers.

22. The storage system of claim 19 , further comprising:

CRC reordering decode circuitry to, in response to a data read command from the host domain to read the data payload from the storage device, reassign a shifted CRC code to the originally paired data segment;

CRC decode circuitry to decode a reassigned CRC code for each respective one of the plurality of data segments to determine a first data integrity status; and

ECC decode circuitry to decode the ECC code of each sector-length portion to determine a second data integrity status.

23. The storage system of claim 17 , further comprising:

CRC reordering decode circuitry to, in response to a data read command from the host domain to read the data payload from the storage device, reassign a shifted CRC code to the originally paired data segment; and

CRC decode circuitry to decode a reassigned CRC code for each data segment to determine a data integrity status.

24. The storage system of claim 17 , wherein the host data segmentation circuitry to divide the data payload by 2 N ; where N is a whole number.