Multilevel memory bus system
The present invention relates to a multilevel memory bus system for transferring information between at least one DMA controller and at least one solid-state semiconductor memory device, such as NAND flash memory devices or the like. This multilevel memory bus system includes at least one DMA controller coupled to an intermediate bus; a flash memory bus; and a flash buffer circuit between the intermediate bus and the flash memory bus. This multilevel memory bus system may be disposed to support: an n-bit wide bus width, such as nibble-wide or byte-wide bus widths; a selectable data sampling rate, such as a single or double sampling rate, on the intermediate bus; a configurable bus data rate, such as a single, double, quad, or octal data sampling rate; CRC protection; an exclusive busy mechanism; dedicated busy lines; or any combination of these.
1. A storage system, comprising:
a local processing system including a local processor connected to a first endpoint of a local bus and a local memory connected to a second endpoint of the local bus;
a host interface connected between a third endpoint of the local bus and a host system wherein the host interface is configured to receive memory transaction requests from the host system;
a flash memory controller connected between a fourth endpoint of the local bus and an intermediate bus configured to operate in accordance with an intermediate bus clock signal, wherein the intermediate bus includes a first data path and the first data path has a first bit width;
a plurality of flash buffers and a corresponding plurality of flash memory banks, wherein each of the flash buffers is connected to the intermediate bus and further connected to a corresponding one of the flash memory banks by a corresponding flash memory bus, wherein each flash memory bus is configured to operate in accordance with a flash bus clock signal and each flash memory bus includes a second data path having a second bit width; and
wherein a frequency of the intermediate bus signal is greater than a frequency of the flash bus clock signal and wherein the second bit width is greater than the first bit width.
2. The storage system of claim 1 , wherein a data throughput of the intermediate bus differs from a data throughput of the flash memory busses and wherein the flash buffers are sufficiently sized and configured to enable the intermediate bus and the flash memory busses to operate with their respective maximum supported clock signal frequencies.
3. The storage system of claim 1 , wherein a ratio of the frequency of the intermediate bus clock signal to the frequency of the flash bus clock signal is an integer selected from: 4 and 8.
4. The storage system of claim 3 , wherein the flash memory controller includes one or more state machines, wherein each of the one or more state machines is configured to generate command, address, and data information in response to a memory transaction request.
5. The storage system of claim 4 , wherein the number of state machines in the flash memory controller is equal to the ratio of the frequency of the intermediate bus clock signal to the frequency of the flash bus clock signal.
6. The storage system of claim 4 , wherein a throughput ratio, comprising a ratio of a data throughput of the intermediate bus to a data throughput of each flash memory bus, is determined in accordance with the ratio of the frequency of the intermediate bus clock signal to the frequency of the flash bus clock signal.
7. The storage system of claim 6 , wherein a data throughput of the intermediate bus is further in accordance with a data sampling rate, wherein the data sampling rate is indicative of how many times data is sampled during a cycle of the intermediate bus clock signal.
8. A storage system, comprising:
a flash memory controller connected between one of a plurality of endpoints of a local bus and an intermediate bus, wherein the intermediate bus is configured to operate in accordance with an intermediate bus clock signal, wherein the intermediate bus includes an intermediate data path and the intermediate data path has a first width wherein the plurality endpoints include a first endpoint connected to a local processor, a second endpoint connected to a local memory, and a third endpoint connected to a host interface;
a plurality of flash buffers and a corresponding plurality of flash memory banks, wherein each of the flash buffers is connected to the intermediate bus and further connected to a corresponding one of the flash memory banks by a corresponding flash memory bus, wherein each flash memory bus is configured to operate in accordance with a flash bus clock signal and each flash memory bus includes a second data path having a second bit width; and
wherein a frequency of the intermediate bus signal is greater than a frequency of the flash bus clock signal and wherein the second bit width is greater than the first bit width.
9. The storage system of claim 8 , wherein a data throughput of the intermediate bus differs from a data throughput of the flash memory busses wherein the flash buffers are sufficiently sized and configured to enable the intermediate bus and the flash memory busses to operate with their respective maximum supported clock signal frequencies.
10. The storage system of claim 8 , wherein a a ratio of the frequency of the intermediate bus clock signal to the frequency of the flash bus clock signal is an integer selected from: 4 and 8.
11. The storage system of claim 10 , wherein a throughput ratio, comprising a ratio of a data throughput of the intermediate bus to a data throughput of each flash memory bus, is determined in accordance with the ratio of the frequency of the intermediate bus clock signal to the frequency of the flash bus clock signal.
12. The storage system of claim 11 , wherein the number of state machines in the flash memory controller is equal to the ratio of the frequency of the intermediate bus clock signal to the frequency of the flash bus clock signal.
13. The storage system of claim 11 , wherein a throughput ratio, comprising a ratio of the data throughput of the intermediate bus to a data throughput of each flash memory bus, is equal to the ratio of the frequency of the intermediate bus clock signal to the frequency of the flash bus clock signal.
14. The storage system of claim 13 , wherein the data throughput of the intermediate bus is further in accordance with a data sampling rate, wherein the data sampling rate is indicative of how many times data is sampled during a cycle of the intermediate bus clock signal.
15. The storage device of claim 8 , further including a dedicated busy line for each of the plurality of flash memory devices.
16. The storage device of claim 8 , further including: an exclusive busy mechanism including a single-bit shared busy line of the intermediate bus, wherein the single-bit shared busy line is connected between the flash memory controller and each of the plurality of flash buffers.
17. The storage device of claim 16 , wherein the exclusive bus mechanism includes a plurality of multiplexers corresponding to the plurality of flash buffers wherein each multiplexer receives a dedicated busy line from each flash memory device associated with a corresponding flash buffer and wherein each multiplexer receives a select input from a counter.