Programmable event driven yield mechanism which may activate other threads
Method, apparatus, and program means for a programmable event driven yield mechanism that may activate other threads. In one embodiment, an apparatus includes execution resources to execute a plurality of instructions and a monitor to detect a condition indicating a low level of progress. The monitor can disrupt processing of a program by transferring to a handler in response to detecting the condition indicating a low level of progress. In another embodiment, thread switch logic may be coupled to a plurality of event monitors which monitor events within the multithreading execution logic. The thread switch logic switches threads based at least partially on a programmable condition of one or more of the performance monitors.
1. A processor comprising:
execution resources to execute program instructions;
a monitor to detect conditions associated with the execution resources,
the monitor including multiple monitor counters,
at least one of the monitor counters programmable by software to count occurrences of a microarchitectural event selected from multiple events, wherein the at least one monitor counter is programmed to monitor a cache miss event by setting a first set of one or more bits;
wherein the monitor is to detect the cache miss event based on the at least one monitor counter reaching a count; and
wherein, in response to the at least one monitor counter reaching the count and a second set of one or more bits indicating that what is monitored by the at least one monitor counter is unmasked, execution of the program instructions is to be redirected to an address stored in a first register.
2. The processor of claim 1 wherein the monitor is further configured to detect at least one low progress indicating condition other than the cache miss event.
3. The processor of claim 1 wherein a low progress indicating condition is indicated by a count of microarchitectural events.
4. The processor of claim 1 wherein the monitor comprises a processor performance monitor readable by a processor instruction.
5. The processor of claim 1 wherein redirection to the address is to be performed by an event handler routine stored in a computer readable medium.
6. The processor of claim 5 wherein the execution resources comprise multithreaded execution circuitry capable of executing a plurality of threads.
7. The processor of claim 1 wherein the monitor is context sensitive.
8. The processor of claim 1 wherein the software comprises a user program.
9. The processor of claim 1 wherein the monitor is programmable by a user program executed at a privilege level lower than a privilege level of an operating system and wherein the cache miss event is at least partially caused by the user program.
10. The processor of claim 9 wherein the privilege level comprises a ring three privilege level.