Method and structure to reduce cell width in integrated circuits

1. An integrated circuit comprising:

a semiconductor substrate;

an active zone extending in a first direction;

a spacer of insulating materials extending in a second direction perpendicular to the first direction, the spacer dividing the active zone into a first part and a second part along the spacer protruding into the semiconductor substrate, with the first part and the second part being conductively isolated from each other by the spacer;

a first transistor, in the first part of the active zone, having two active regions separated by a channel region;

a second transistor, in the second part of the active zone, having two active regions separated by a channel region;

a first gate-strip and a second gate-strip each extending in the second direction, wherein the first gate-strip covers the channel region of the first transistor and the second gate-strip covers the channel region of the second transistor;

a first conductive segment and a second conductive segment each extending in the second direction and in a middle layer, wherein the middle layer is a layer between the semiconductor substrate and a metal layer, the metal layer overlying an inter layer dielectric layer on the semiconductor substrate;

wherein the first conductive segment forms conductive contact with a first one of the two active regions in the first transistor, and the second conductive segment forms conductive contact with a first one of the two active regions in the second transistor; and

wherein the spacer joins the first conductive segment and the second conductive segment while electrically isolating the first conductive segment from the second conductive segment.

2. The integrated circuit of claim 1 , further comprising:

a first cell having at least one logic function;

a second cell having at least one logic function; and

wherein the first transistor is inside the first cell and the second transistor is located inside the second cell.

3. The integrated circuit of claim 2 , wherein the spacer is located at a boundary separating the first cell from the second cell.

4. The integrated circuit of claim 1 , further comprising:

a third conductive segment and a fourth conductive segment each extending in the second direction, wherein the third conductive segment covers a second one of the two active regions in the first transistor and the fourth conductive segment covers a second one of the two active regions in the second transistor.

5. The integrated circuit of claim 4 , further comprising:

a third gate-strip, extending in the second direction, over the first part of the active zone; and

wherein the third conductive segment is between the third gate-strip and the first gate-strip.

6. The integrated circuit of claim 5 , wherein the separation between a middle line of the first gate-strip and a middle line of the second gate-strip is 1.5 times the separation between the middle line of the first gate-strip and a middle line of the third gate-strip.

7. An integrated circuit comprising:

a semiconductor substrate;

a p-type active zone and an n-type active zone forming two parallel active zones each extending in a first direction;

a spacer of insulating materials extending in a second direction perpendicular to the first direction, the spacer dividing each of the two parallel active zones into a first part and a second part, the spacer protrudes into the semiconductor substrate and conductively isolates the first part from the second part in each of the two parallel active zones, with the first part at a first side of the spacer and the second part at a second side of the spacer;

a first gate-strip, extending in the second direction, over at least one of the two parallel active zones at the first side of the spacer;

a second gate-strip, extending in the second direction, over at least one of the two parallel active zones at the second side of the spacer;

a first conductive segment, extending in the second direction, forming active region contact with at least one of the two parallel active zones at the first side of the spacer;

a second conductive segment, extending in the second direction, forming active region contact with at least one of the two parallel active zones at the second side of the spacer; and

wherein the spacer joins the first conductive segment and the second conductive segment while electrically isolating the first conductive segment from the second conductive segment, each of the first conductive segment and second conductive segment in a middle layer between the semiconductor substrate and a metal layer, with the metal layer overlying an inter layer dielectric layer on the semiconductor substrate.

8. The integrated circuit of claim 7 , wherein each of the first gate-strip and the second gate-strip covers both of the two parallel active zones.

9. The integrated circuit of claim 7 , wherein each of the first conductive segment and the second conductive segment covers both of the two parallel active zones.

10. The integrated circuit of claim 7 , further comprising:

a first cell having at least one logic function;

a second cell having at least one logic function; and

wherein the first conductive segment and the first gate-strip are inside the first cell, and the second conductive segment and the second gate-strip are inside the second cell.

11. The integrated circuit of claim 10 , wherein the spacer is at a boundary separating the first cell from the second cell.

12. The integrated circuit of claim 7 , comprising:

a third conductive segment extending in the second direction, the third conductive segment aligned with the first conductive segment along the second direction at the first side of the spacer; and

wherein the first conductive segment covers one of the two parallel active zones at the first side of the spacer, the third conductive segment covers the other one of the two parallel active zones at the first side of the spacer, and the second conductive segment covers both of the two parallel active zones at the second side of the spacer.

13. The integrated circuit of claim 12 , wherein the spacer joins the third conductive segment and the second conductive segment while electrically isolating the third conductive segment from the second conductive segment.

14. The integrated circuit of claim 7 , further comprising:

a third conductive segment extending in the second direction, the third conductive segment aligned with the first conductive segment along the second direction at the first side of the spacer;

a fourth conductive segment extending in the second direction, the fourth conductive segment aligned with the second conductive segment along the second direction at the second side of the spacer; and

wherein the first conductive segment covers one of the two parallel active zones at the first side of the spacer, the third conductive segment covers the other one of the two parallel active zones at the first side of the spacer, the second conductive segment covers one of the two parallel active zones at the second side of the spacer, and the forth conductive segment covers the other one of the two parallel active zones at the second side of the spacer.

15. The integrated circuit of claim 14 , wherein the spacer joins the third conductive segment and the fourth conductive segment while electrically isolating the third conductive segment from the fourth conductive segment.

16. The integrated circuit of claim 7 , further comprising:

a third conductive segment, extending in the second direction, over at least one of the two parallel active zones at the first side of the spacer, wherein the first gate-strip is between the first conductive segment and the third conductive segment; and

a third gate-strip, extending in the second direction, over at least one of the two parallel active zones at the first side of the spacer, wherein the third conductive segment is between the third gate-strip and the first gate-strip.

17. The integrated circuit of claim 7 , further comprising:

a third gate-strip, extending in the second direction, over at least one of the two parallel active zones at the first side of the spacer; and

wherein the separation between a middle line of the first gate-strip and a middle line of the second gate-strip is 1.5 times the separation between the middle line of the first gate-strip and a middle line of the third gate-strip.

18. The integrated circuit of claim 7 , further comprising:

a third gate-strip, extending in the second direction, over at least one of the two parallel active zones at the first side of the spacer; and

a plurality of routing lines, in the metal layer overlying the inter layer dielectric layer, extending in the second direction, wherein a pitch distance between two neighboring routing lines is 0.5 times a pitch distance between the first gate-strip and the third gate-strip.

19. A method of generating, by a processor, a layout design of an integrated circuit, the method comprising:

creating an active zone pattern, extending in a first direction, that specifies an active zone in a semiconductor substrate;

creating two middle layer patterns, extending in the second direction perpendicular to the first direction, over the active zone pattern, wherein the two middle layer patterns specify two conductive segments in a middle layer, wherein the middle layer is a layer between the semiconductor substrate and a metal layer, with the metal layer overlying an inter layer dielectric layer on the semiconductor substrate;

creating a spacer pattern, extending in the second direction, jointing the two middle layer patterns, and dividing the active zone pattern into a first part and a second part; and

wherein the spacer pattern specifies a spacer of insulating materials that conductively isolates the two conductive segments from each other in the middle layer and conductively isolates the first part of the active zone from the second part of the active zone in the semiconductor substrate.

20. The method of claim 19 , further comprising:

creating a first cell pattern that specifies a first cell having at least one logic function, the first cell pattern having therein one of the two middle layer patterns;

creating a second cell pattern that specifies a second cell having at least one logic function, the second cell pattern having therein the other one of the two middle layer patterns;

wherein the spacer pattern is at a boundary between the first cell pattern and the second cell pattern.