Semiconductor device, memory system, and operating method of semiconductor device

1. A semiconductor device comprising:

a memory string including a plurality of memory cells, a plurality of select transistors, and one or more dummy transistors coupled between the plurality of memory cells and the plurality of select transistors;

a plurality of word lines respectively coupled to the plurality of memory cells;

one or more dummy word lines coupled to the one or more dummy transistors; and

a plurality of select lines respectively coupled to the plurality of select transistors,

wherein, when a program voltage is applied to a selected dummy word line among the one or more dummy word lines, a first dummy word line voltage is applied to a select line adjacent to the one or more dummy word lines, among the plurality of select lines.

2. The semiconductor device of claim 1 ,

wherein a second dummy word line voltage is applied to one or more unselected dummy word line among the one or more dummy word lines.

3. The semiconductor device of claim 2 , wherein the first dummy word line voltage has a level lower than that of the second dummy word line voltage.

4. The semiconductor device of claim 2 , wherein the first and second dummy word line voltages have different voltage levels from each other, and each of the different voltage levels is greater as the unselected dummy word line and the select line become closer to the plurality of word lines.

5. The semiconductor device of claim 1 , wherein a ground voltage is applied to other select lines in which the first dummy word line voltage is not applied among the plurality of select lines.

6. The semiconductor device of claim 1 , wherein, when the program voltage is applied to the selected dummy word line, a pass voltage is applied to the plurality of word lines.

7. The semiconductor device of claim 6 , wherein the first dummy word line voltage has a lower voltage level than that of the pass voltage.

8. A method for operating a semiconductor device including a plurality of memory cells, a plurality of select transistors, and a plurality of dummy transistors coupled between the plurality of memory cells and the plurality of select transistors, a plurality of word lines respectively coupled to the plurality of memory cells, a plurality of dummy word lines respectively coupled to the plurality of dummy transistors, and a plurality of select lines respectively coupled to the plurality of select transistors, the method comprising:

applying a program voltage to a selected dummy word line among the plurality of dummy word lines; and

applying a first dummy word line voltage to a select line adjacent to the plurality of dummy word lines, among the plurality of select lines.

9. The method of claim 8 , further comprising applying a second dummy word line voltage to one or more unselected dummy word lines among the plurality of dummy word lines.

10. The method of claim 9 , wherein the first dummy word line voltage has a level lower than that of the second dummy word line voltage.

11. The method of claim 9 , wherein the first and second dummy word line voltages have different voltage levels from each other, and each of the different voltage levels is greater as the unselected dummy word line and the select line become closer to the plurality of word lines.

12. The method of claim 8 , further comprising:

applying a pass voltage to the plurality of word lines respectively coupled to the plurality of memory cells; and

applying a ground voltage to other select lines in which the first dummy word line voltage is not applied among the plurality of select lines.

13. The method of claim 12 , wherein the first dummy word line voltage has a voltage level lower than that of the pass voltage.

14. A memory system comprising:

a memory device including a memory string including a plurality of memory cells, a plurality of select transistors, and one or more dummy transistors coupled between the plurality of memory cells and the plurality of select transistors, a plurality of word lines respectively coupled to the plurality of memory cells, one or more dummy word lines coupled to the one or more dummy transistors, and a plurality of select lines respectively coupled to the plurality of select transistors; and

a controller configured to, in a program operation, control the memory device to apply a program voltage to a selected dummy word line among the one or more dummy word lines, and apply a first dummy word line voltage to a select line adjacent to the one or more dummy word lines, among the plurality of select lines.

15. The memory system of claim 14 , wherein the controller determines whether program data is cold data or hot data, and controls the memory device to, when it is determined that the program data is the cold data, select a line among the plurality of word lines and the one or more dummy word lines and apply the program voltage to the selected line.

16. The memory system of claim 15 , wherein, in a garbage collection operation, the controller determines valid data as the cold data or the hot data.

17. The memory system of claim 15 , wherein the controller controls the memory device to, when it is determined that the program data is the hot data, select a line among the plurality of word lines and apply the program voltage to the selected line.

18. The memory system of claim 14 , wherein the controller determines an order of priority of performance and data capacity according to usage of the memory device, and controls the memory device to, when a priority of the data capacity is higher than a priority of the performance, select a line among the plurality of word lines and the one or more dummy word lines and apply the program voltage to the selected line.

19. The memory system of claim 18 , wherein the controller controls the memory device to, when a priority of the performance is higher that a priority of the data capacity, select a line among the plurality of word lines and apply the program voltage to the selected line.