Self aligned via and method for fabricating the same
A self aligned via and a method for fabricated a semiconductor device using a double-trench constrained self alignment process to form the via. The method includes forming a first trench and depositing a first metal into the first trench. Afterwards, the process includes depositing a dielectric layer over the first metal such that a top surface of the dielectric layer is at substantially the same level as the top surface of the first trench. Next, a second trench is formed and a via is formed by etching the portion of the dielectric layer exposed by the overlapping region between the first trench and the second trench. The via exposes a portion of the first metal and a second metal is deposited into the second trench such that the second metal is electrically coupled to the first metal.
1. A method for fabricating a semiconductor device, comprising:
depositing a first metal into a first trench of a first dielectric layer such that a top surface of the first metal is below a top surface of the first dielectric layer;
removing the first dielectric layer to expose the first metal on the top surface of the first metal and two sides of the first metal;
depositing a second dielectric layer over the first metal such that the second dielectric layer surrounds the top and the two sides of the first metal;
depositing a third dielectric layer over the first dielectric layer and the second dielectric layer;
etching the third dielectric layer to create a second trench that exposes a portion of the first dielectric layer and a portion of the second dielectric layer; and
etching the exposed portion of the second dielectric layer to expose a portion of the first metal to create a via to the first metal; and
wherein an etching ratio of a material of the second dielectric layer is greater than an etching ratio of a material of the third dielectric layer.
2. The method of claim 1 , further comprising depositing a second metal into the second trench such that the second metal is electrically coupled to the first metal.
3. The method of claim 1 , wherein the first dielectric layer and the second dielectric layer have different etching sensitivities.
4. The method of claim 1 , wherein the third dielectric layer and the second dielectric layer have different etching sensitivities.
5. The method of claim 1 , wherein the third dielectric layer and the first dielectric layer are the same material.
6. The method of claim 1 , wherein the first metal represents a first conductive path on a certain layer of the semiconductor device and the second metal represents a second conductive path on a different layer of the semiconductor device coupled to the first conductive path by the via formed by etching the second dielectric layer.
7. The method of claim 1 , wherein the first trench extends in a first direction and the second trench extends in a second direction that is different from the first direction.
8. The method of claim 5 , wherein the first direction and the second direction are substantially perpendicular to one another.
9. The method of claim 1 , wherein at least one of the first dielectric layer, the second dielectric layer, and the third dielectric layer is a silicon oxide layer, silicon carbon oxide, silicon nitride layer, silicon carbon nitride layer, or an aluminum oxide layer.
10. The method of claim 1 , wherein a height of the via is between 0.2 and 0.8 times a metal pitch of the semiconductor device.
11. The method of claim 1 , wherein the first metal and the second metal are at least one of copper, cobalt, tungsten, nickel, and combinations thereof.
12. A method for fabricating a semiconductor device, comprising:
providing a first dielectric layer;
etching the first dielectric layer to create a first trench;
depositing a first metal into the first trench;
removing the first dielectric material;
depositing a second dielectric layer over the first metal such that the second dielectric layer surrounds a top and two sides of the first metal;
depositing a third dielectric layer over and surrounding the second dielectric layer and the first metal;
etching the third dielectric layer to create a second trench that exposes a portion of the second dielectric layer and a portion of lower layers of the third dielectric layer;
etching the exposed portion of the second dielectric layer to expose a portion of the first metal; and
depositing a second metal into the second trench such that the second metal is electrically coupled to the first metal; and
wherein an etching ratio of a material of the second dielectric layer is greater than an etching ratio of a material of the third dielectric layer.
13. The method of claim 12 , wherein the third dielectric layer and the second dielectric layer have different etching sensitivities.
14. The method of claim 12 , wherein the first metal represents a first conductive path on a certain layer of the semiconductor device and the second metal represents a second conductive path on a different layer of the semiconductor device coupled to the first conductive path by a via formed by etching the second dielectric layer.
15. The method of claim 12 , wherein the first trench extends in a first direction and the second trench extends in a second direction that is different from the first direction.
16. The method of claim 15 , wherein the first direction and the second direction are substantially perpendicular to one another.
17. The method of claim 12 , wherein at least one of the first dielectric layer, the second dielectric layer, and the third dielectric layer is a silicon oxide layer, silicon carbon oxide, silicon nitride layer, silicon carbon nitride layer, or an aluminum oxide layer.
18. A method for fabricating a semiconductor device, comprising:
forming a first trench in a first dielectric layer;
depositing a first metal into the first trench such that a top surface of the first metal is below a top surface of the first trench;
depositing a second dielectric layer over the first metal such that the second dielectric layer surrounds a top of the first metal;
depositing a third dielectric layer over and surrounding the second dielectric layer and the first metal;
forming a second trench in the third dielectric layer, the second trench exposes a portion of the second dielectric layer and a portion of the third dielectric layer;
forming a via by etching the exposed portion of the second dielectric layer to expose a portion of the first metal; and
depositing a second metal into the second trench such that the second metal is electrically coupled to the first metal; and
wherein an etching ratio of a material of the second dielectric layer is greater than an etching ratio of a material of the third dielectric layer.
19. The method of claim 18 , wherein the first metal represents a first conductive path on a certain layer of the semiconductor device and the second metal represents a second conductive path on a different layer of the semiconductor device coupled to the first conductive path by the via formed by etching the second first dielectric layer.
20. The method of claim 18 , wherein the third dielectric layer and the second dielectric layer have different etching sensitivities.