Sawn leadless package having wettable flank leads
A method of forming a leadless packaged semiconductor device. First partial sawing leads is performed on a bottom side of an in-process leadless semiconductor package having a leadframe including die pad with a semiconductor chip thereon, and leads defining top and bottom surfaces and having an inner end and an outer end having a bottom corner region. Conductive bond wires connect to and extending between bond pads on the chip and respective leads, a mold compound is around the die pad, leads, chip, and conductive bond wires while exposing the bottom surface and outer end. The first sawing completely severs the leads while forming only a partial cut in the mold compound. A de-flash process is applied to the bottom side. The second sawing aligned to the partial cuts reaches the partial cuts to complete singulation of the package, wherein the second sawing does not touch the leads.
1. A semiconductor package, comprising:
a leadframe including a die pad;
a semiconductor chip attached to said die pad;
said leadframe including a plurality of leads extending about said die pad, each of said leads defining an opposing top and bottom surface and having an inner end, an outer end, wherein said bottom surface and said outer end collectively define a bottom corner region, at least one conductive bond wire electrically connected to and extending between a bond pad on said semiconductor chip and a respective one of said leads, and a mold compound around said die pad, said leads, said semiconductor chip, and said conductive bond wire such that said bottom surface and said outer end as well as sidewalls of said mold compound are each exposed;
wherein said sidewalls include a first tone for its bottom portion compared to a second tone different from said first tone for its top portion.
2. The semiconductor package of claim 1 , wherein said bottom corner region includes a recess with respect to said outer end.
3. The semiconductor package of claim 1 , wherein said semiconductor package comprises a Small Outline No-Lead (SON), a Dual Flat No-Lead (DFN) or a Quad Flat No-Lead (QFN) package.
4. The semiconductor package of claim 1 , wherein said die pad is exposed from said mold compound.
5. The semiconductor package of claim 1 , wherein said bottom portion of said sidewalls extends out 0.025 mm beyond said top portion of said sidewalls.
6. A semiconductor package, comprising:
a leadframe including a die pad;
a semiconductor chip attached to said die pad;
said leadframe including a plurality of leads extending about said die pad, each of said leads defining an opposing top and bottom surface and having an inner end, an outer end, wherein said bottom surface and said outer end collectively define a bottom corner region, at least one conductive bond wire electrically connected to and extending between a bond pad on said semiconductor chip and a respective one of said leads, and a mold compound around said die pad, said leads, said semiconductor chip, and said conductive bond wire such that said bottom surface and said outer end as well as sidewalls of said mold compound are each exposed;
wherein said bottom portion of said sidewalls is parallel to and extends out beyond said top portion of said sidewalls.
7. The semiconductor package of claim 6 , wherein said bottom corner region includes a recess with respect to said outer end.
8. The semiconductor package of claim 6 , wherein said leadless semiconductor package comprises a Small Outline No-Lead (SON), a Dual Flat No-Lead (DFN) or a Quad Flat No-Lead (QFN) package.
9. The semiconductor package of claim 6 , wherein said die pad is exposed from said mold compound.
10. The semiconductor package of claim 6 , wherein said bottom portion of said sidewalls extends out 0.025 mm beyond said top portion of said sidewalls.
11. A semiconductor package, comprising:
a leadframe including a die pad;
a semiconductor chip attached to said die pad;
said leadframe including a plurality of leads extending about said die pad, each of said leads defining an opposing top and bottom surface and having an inner end, an outer end, wherein said bottom surface and said outer end collectively define a bottom corner region, at least one conductive bond wire electrically connected to and extending between a bond pad on said semiconductor chip and a respective one of said leads, and a mold compound around said die pad, said leads, said semiconductor chip, and said conductive bond wire such that said bottom surface and said outer end as well as sidewalls of said mold compound are each exposed;
wherein said sidewalls include a first tone for its bottom portion compared to a second tone different from said first tone for its top portion, and said bottom portion of said sidewalls extend out beyond said top portion of said sidewalls.
12. The semiconductor package of claim 11 , wherein said bottom corner region includes a recess with respect to said outer end.
13. The semiconductor package of claim 11 , wherein said semiconductor package comprises a Small Outline No-Lead (SON), a Dual Flat No-Lead (DFN) or a Quad Flat No-Lead (QFN) package.
14. The semiconductor package of claim 11 , wherein said die pad is exposed from said mold compound.
15. The semiconductor package of claim 11 , wherein said bottom portion of said sidewalls extends out 0.025 mm beyond said top portion of said sidewalls.