Solid-state image pickup device to increase an area efficiency of a silicon interface on the transistor element side and electronic apparatus
A PD unit has a Tr-side Si/SiO2 interface formed to be p-type, and has an embedded PD. The PD, which is n-type, performs photoelectric conversion, and accumulates an electrical charge. A TG transfers the electrical charge accumulated in the PD to an FD. An Amp is connected to the FD. An RST is connected to a Reset Drain (RD), and resets the FD. An FDG is a conversion-efficiency switching switch. An FC is a MOS capacitance (gate electrode) that is connected to the FDG. A SEL selects a pixel that outputs a signal.
1. A solid-state image pickup device, comprising:
a photodiode;
a capacitance on the photodiode;
a floating diffusion;
a reset transistor; and
a specific transistor connected between the capacitance and the floating diffusion, wherein
the capacitance is connected to the floating diffusion and the capacitance is set at a first electric potential, when the specific transistor is switched on and a reset drain electric potential is at a first level, and
in a light exposure time period:
the capacitance is set at a second electric potential through the reset transistor, when the reset drain electric potential is at a second level and the specific transistor is switched on, and
the capacitance is held at the set second electric potential, when the specific transistor is switched off subsequent to the set of the capacitance at the second electric potential, wherein
the second level of the reset drain electric potential is lower than the first level of the reset drain electric potential, and
the second electric potential of the capacitance is lower than the first electric potential of the capacitance.
2. The solid-state image pickup device according to claim 1 , wherein the capacitance is a metal oxide semiconductor (MOS) capacitance that comprises a poly.
3. The solid-state image pickup device according to claim 1 , wherein the capacitance is an n+ electrode on a hole accumulation layer.
4. The solid-state image pickup device according to claim 1 , wherein the capacitance is used for switching a conversion efficiency.
5. The solid-state image pickup device according to claim 1 , wherein
the photodiode is embedded into a deep region of a substrate, and
a part of the substrate is used as a junction capacitance, based on the embedded photodiode.
6. The solid-state image pickup device according to claim 1 , wherein in a case of pixel sharing in which the photodiode is shared, the photodiode is allocated to the capacitance, the specific transistor, or a well contact.
7. The solid-state image pickup device according to claim 1 , wherein
the capacitance is a first metal oxide semiconductor (MOS) capacitance,
a MOS gate of the first MOS capacitance comprises one of a high concentration p-type silicon or a high concentration n-type silicon, and
a linearity of an output corresponding to the first MOS capacitance is higher than a linearity of an output corresponding to a second MOS capacitance having one of a low concentration p-type silicon or a low concentration n-type silicon.
8. The solid-state image pickup device according to claim 7 , wherein when the MOS gate is the high concentration p-type silicon, a gate electrode of the MOS gate comprises one of p+polySi, PtSi, or NiSi.
9. The solid-state image pickup device according to claim 7 , wherein when the MOS gate is the high concentration p-type silicon, a gate insulating film for the MOS gate comprises one of HfO2 or Al2O3.
10. The solid-state image pickup device according to claim 7 , wherein when the MOS gate is the high concentration n-type silicon, a gate electrode of the MOS gate comprises one of n+polySi, TaN, or TiN.
11. The solid-state image pickup device according to claim 7 , wherein when the MOS gate is the high concentration n-type silicon, a gate insulating film for the MOS gate comprises one of Y2O3 or La2O3.
12. The solid-state image pickup device according to claim 7 , wherein the linearity of the output corresponding to the first MOS capacitance is evaluated to correct a bend part of the output, corresponding to the first MOS capacitance, in a stage subsequent to signal lines of a pixel array.
13. The solid-state image pickup device according to claim 12 , wherein linearity information is recorded for the correction of the bend part of the output corresponding to the first MOS capacitance.
14. The solid-state image pickup device according to claim 1 , wherein the solid-state image pickup device is backside-illumination type.
15. An electronic apparatus, comprising:
a solid-state image pickup device including:
a photodiode;
a capacitance on the photodiode;
a floating diffusion;
a reset transistor; and
a specific transistor connected between the capacitance and the floating diffusion, wherein
the capacitance is connected to the floating diffusion and the capacitance is set at a first electric potential, when the specific transistor is switched on and a reset drain electric potential is at a first level, and
in a light exposure time period:
the capacitance is set at a second electric potential through the reset transistor, when the reset drain electric potential is at a second level and the specific transistor is switched on, and
the capacitance is held at the set second electric potential, when the specific transistor is switched off subsequent to the set of the capacitance at the second electric potential, wherein
the second level of the reset drain electric potential is lower than the first level of the reset drain electric potential, and
the second electric potential of the capacitance is lower than the first electric potential of the capacitance;
a signal processing circuit that configured to process an output signal output from the solid-state image pickup device; and
an optical system configured to receive incident light into the solid-state image pickup device.