Display device and interface operation thereof
An electronic device includes; a timing controller that generates a command to-be-sent to a display driver integrated circuit (DDI) selected from among a plurality of display driver integrated circuits (DDIs) connected to the timing controller through data lines and a shared channel The DDI is selected by a DDI control signal transferred from the timing controller to the DDI through a corresponding data line among the data lines, and the command is transferred from the timing controller to the DDI through the shared channel.
1. A display driver circuit (DDI) comprising a circuit configured to receive a DDI control signal including a clock training pattern via a first channel at a first data transfer rate, to perform a training operation based on the clock training pattern,
wherein the DDI is configured to receive a training signal that defines a training period for the DDI via a second channel from a timing controller,
wherein the DDI is configured to receive a command signal via a third channel at a second data transfer rate from the timing controller,
wherein the first data transfer rate is faster than the second data transfer rate,
wherein the DDI control signal defines a chip selection condition,
wherein the first to third channels are different from each other, and
wherein the DDI is configured to connect to the timing controller via the first channel in a point to point manner.
2. The DDI of claim 1 , wherein the DDI control signal includes a differential signal including a positive signal and a negative signal.
3. The DDI of claim 1 , wherein the DDI is configured to receive the training signal at a third data transfer rate slower than the first data transfer rate.
4. The DDI of claim 3 , wherein the DDI is configured to transfer state information of the DDI via the third channel to the timing controller.
5. The DDI of claim 4 , wherein the state information includes performance information of the DDI.
6. The DDI of claim 1 , wherein the command signal includes one of a write command or a read command.
7. The DDI of claim 6 , wherein the DDI recognizes whether one of the write command or the read command is pending or not using signals received from the second channel and the third channel.
8. The DDI of claim 1 , wherein the circuit includes one of a delay locked loop circuit or a phase locked loop.
9. A display driver circuit (DDI) comprising a circuit configured to receive a DDI control signal including a clock training pattern via a first channel at a first data transfer rate, to perform a training operation based on the clock training pattern,
wherein the DDI is configured to receive a training signal via a first shared channel from a timing controller,
wherein the DDI is configured to receive a command signal via a second shared channel from the timing controller,
wherein the DDI is configured to receive a write command via the second shared channel when the training signal changes from a first state to a second state at time T 1 and the command signal is in the first state at the time T 1 .
10. The DDI of claim 9 , wherein the DDI is configured to transfer state information of the DDI via the second shared channel to the timing controller.
11. The DDI of claim 9 , wherein the DDI is configured to receive the command signal at a second data transfer rate slower than the first data transfer rate.
12. The DDI of claim 9 , wherein the DDI is configured to receive the write command at time T 2 after the command signal changes from the first state to the second state, and
wherein the T 2 is later than the T 1 .
13. The DDI of claim 9 , wherein the DDI control signal includes a differential signal including a positive signal and a negative signal.
14. The DDI of claim 9 , wherein the DDI is configured to connect to the timing controller via the first channel in a point to point manner.
15. The DDI of claim 9 , wherein the circuit is one of a delay locked loop circuit or a phase locked loop.
16. The DDI of claim 9 , wherein the DDI control signal defines a chip selection condition.