Ferroelectric memory-based synapses

1. An apparatus comprising:

a first layer and a second layer;

a first gate including first gate portions and a second gate including second gate portions;

wherein the first layer: (a) is monolithic, (b) is between the first gate portions and is also between the second gate portions, and (c) includes a semiconductor material;

wherein the second layer: (a) is between the first layer and at least one of the first gate portions and is also between the first layer and at least one of the second gate portions, and (b) includes oxygen and at least one of hafnium, silicon, yttrium, zirconium, barium, titanium, lead, or combinations thereof;

wherein (a) a first plane intersects the first gate portions and the first and second layers, (b) a second plane intersects the second gate portions and the first and second layers, and (c) the first gate portions are monolithic with each other and the second gate portions are monolithic with each other;

wherein (a) the first layer is included in a synapse, and (b) a weight of the synapse is based on a resistance of the first layer;

wherein the resistance is a variable resistance configured to vary in magnitude of resistance in response to: (a) a first signal to be applied to the first gate, and (b) a second signal to be applied to the second gate;

wherein (a) the variable resistance is further configured to include a number of resistance levels; and (b) the number of resistance levels is proportional to a total number of gates corresponding to the first layer.

2. The apparatus of claim 1 comprising:

an additional first layer and an additional second layer;

an additional first gate including additional first gate portions and an additional second gate including additional second gate portions;

wherein the additional first layer: (a) is monolithic, (b) is between the additional first gate portions and is also between the additional second gate portions, and (c) includes the semiconductor material;

wherein the additional second layer: (a) is between the additional first layer and at least one of the additional first gate portions and is also between the additional first layer and at least one of the additional second gate portions, and (b) includes oxygen and the at least one of hafnium, silicon, yttrium, zirconium, barium, titanium, lead, or combinations thereof;

wherein (a) the first plane intersects the additional first gate portions and the additional first and additional second layers, and (b) the second plane intersects the additional second gate portions and the additional first and additional second layers;

wherein the first layer is not monolithic with the additional first layer.

3. The apparatus of claim 2 comprising a third layer, wherein the third layer: (a) includes a metal; and (b) is coupled to the first layer and the additional first layer.

4. The apparatus of claim 3 comprising a switching device having a node coupled to the first layer.

5. The apparatus of claim 4 comprising an amplifier, the amplifier including a node coupled to the third layer.

6. The apparatus of claim 4 comprising an analog circuit, wherein the analog circuit:

includes a node coupled to the third layer; and

is configured to apply a non-linear function to an output from the third layer.

7. The apparatus of claim 5 wherein the additional first layer is included in an additional synapse.

8. The apparatus of claim 7 wherein an additional weight of the additional synapse is based on an additional resistance of the additional first layer.

9. The apparatus of claim 8 comprising a neuron corresponding to the synapse, the neuron including the amplifier.

10. The apparatus of claim 9 wherein the neuron includes the third layer.

11. The apparatus of claim 3 wherein the third layer is configured to combine output current from the first layer with additional output current from the additional first layer.

12. The apparatus of claim 2 comprising:

a supplemental first layer and a supplemental second layer;

a supplemental first gate including supplemental first gate portions and a supplemental second gate including supplemental second gate portions;

wherein the supplemental first layer: (a) is monolithic, (b) is between the supplemental first gate portions and is also between the supplemental second gate portions, and (c) includes the semiconductor material;

wherein the supplemental second layer: (a) is between the supplemental first layer and at least one of the supplemental first gate portions and is also between the supplemental first layer and at least one of the supplemental second gate portions, and (b) includes oxygen and the at least one of hafnium, silicon, yttrium, zirconium, barium, titanium, lead, or combinations thereof;

wherein (a) the first plane intersects the supplemental first gate portions and the supplemental first and supplemental second layers, and (b) the second plane intersects the supplemental second gate portions and the supplemental first and supplemental second layers;

wherein the first layer is not monolithic with the supplemental first layer;

wherein (d)(i) the first gate and the additional first gate are configured to operate simultaneously, and (d)(ii) the first gate and the supplemental first gate are configured to operate non-simultaneously.

13. The apparatus of claim 1 , wherein (a) the first gate is included in a first memory cell that has no more than two possible memory states, (b) the second gate is included in a second memory cell that has no more than two possible memory states, and (c) the first and second memory cells are in series with one another.

14. The apparatus of claim 1 , wherein (a) the first gate is included in a first memory cell that has at least three possible memory states, and (a) the second gate is included in a second memory cell that has at least three possible memory states.

15. The apparatus of claim 1 wherein the second layer is monolithic.

16. The apparatus of claim 1 wherein:

the first gate is included in a first memory cell and the second gate is included in a second memory cell;

the first and second gates are configured to simultaneously write a first memory state to the first memory cell and a second memory state to the second memory cell.

17. The apparatus of claim 1 comprising:

an integrated circuit on a first die, the integrated circuit including the first layer;

a memory on a second die;

the first die and the second die both on a package substrate.

18. The apparatus of claim 17 wherein the integrated circuit comprises a field programmable gate array (FPGA).

19. The apparatus of claim 1 wherein within the first plane the second layer surrounds the first layer.

20. The apparatus of claim 1 wherein the first gate is not a floating gate and the second gate is not a floating gate.