IP Library › Granted Patent US 10,886,329
Granted Patent B2
US 10,886,329 · App. 16/177,692 · Granted Jan 5, 2021

Thermoelectric micro-supercapacitor integrated device and manufacturing method thereof

Inventors: Sang Sig Kim (Seoul, KR); Kyoung Ah Cho (Seoul, KR); Kyung Whan Yang (Suwon-si, KR)
Assignee: Korea University Research and Business Foundation
H01L27/16H01L28/60H01L35/32H01L35/34
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Quick Facts
Patent No.
US 10,886,329
App. No.
16/177,692
Granted
Jan 5, 2021
Kind
B2
Abstract

The present invention provides a thermoelectric micro-supercapacitor integrated device comprising: a thermoelectric power generation module comprising a thermoelectric unit body including a thermoelectric channel interposed between two different heat sources and disposed on a substrate, the thermoelectric channel being composed of an n-type or p-type semiconductor; and a micro-supercapacitor module configured to be operated in cooperation with the thermoelectric power generation module and including a pair of collector electrodes between which an electric potential difference is generated through the thermoelectric channel.

Claims (22)

1. A thermoelectric supercapacitor integrated device comprising:

a thermoelectric power generation module comprising a thermoelectric unit body comprising a thermoelectric channel interposed between two different heat sources and disposed on a substrate, the thermoelectric channel being composed of an n-type or a p-type semiconductor; and

a plurality of supercapacitor modules stacked together in a vertical direction away from a surface of the substrate and configured to be operated in cooperation with the thermoelectric power generation module,

wherein each of the plurality of supercapacitor modules comprises a pair of collector electrodes between which an electric potential difference is generated through the thermoelectric channel.

2. The thermoelectric supercapacitor integrated device according to claim 1 , wherein the thermoelectric unit body of the thermoelectric power generation module comprises:

a high-temperature electrode disposed on the substrate so as to be positioned at a high-temperature side heat source of the two different heat sources;

a pair of low-temperature electrodes disposed on the substrate so as to be positioned at a low-temperature side heat source of the two different heat sources, the low-temperature electrodes being spaced apart from the high-temperature electrode;

a p-type thermoelectric channel configured to connect the high-temperature electrode and the low-temperature electrodes to each other and composed of a p-type semiconductor, and

an n-type thermoelectric channel configured to connect the high-temperature electrode and the low-temperature electrodes to each other and composed of an n-type semiconductor, the n-type thermoelectric channel being disposed spaced apart from the p-type thermoelectric channel.

3. The thermoelectric supercapacitor integrated device according to claim 2 , wherein each of the plurality of miniaturized supercapacitor modules is connected to each of both ends of the low-temperature electrodes.

4. The thermoelectric supercapacitor integrated device according to claim 3 , wherein each of the pair of collector electrodes is connected at one end thereof to an associated one of the pair of low-temperature electrodes, the pair of collector electrodes being disposed spaced apart from each other, and

wherein each of the plurality of supercapacitor modules comprises:

a pair of opposed supercapacitor collectors connected at one ends thereof to the pair of collector electrodes, respectively, and disposed spaced apart from each other; and

a dielectric layer disposed on the supercapacitor collectors.

5. The thermoelectric supercapacitor integrated device according to claim 4 , wherein the pair of opposed supercapacitor collectors are stacked disposed on the low-temperature electrodes and the high-temperature electrode, respectively, when viewed vertically from above the substrate.

6. The thermoelectric supercapacitor integrated device according to claim 5 , wherein each of the plurality of supercapacitor modules comprises an rGO (reduced graphene oxide) active electrode disposed on the pair of opposed supercapacitor collectors.

7. The thermoelectric supercapacitor integrated device according to claim 6 , wherein the pair of opposed supercapacitor collectors, the rGO active electrode, and the dielectric layer are stacked in plural layers, and the pair of opposed supercapacitor collectors are stacked in the vertical direction from the surface of the substrate and connected.

8. The thermoelectric supercapacitor integrated device according to claim 7 , wherein the thermoelectric unit body is disposed in plural numbers in such a manner as to be continuously arranged spaced apart from one another, and the plurality of supercapacitor modules further comprises a connection collector configured to connect the pair of opposed supercapacitor collectors for the thermoelectric unit body.

9. The thermoelectric supercapacitor integrated device according to claim 2 , wherein the thermoelectric unit body is configured such that the pair of low-temperature electrodes, the high-temperature electrode, the p-type thermoelectric channel, and the n-type thermoelectric channel are connected in series with each other.

10. The thermoelectric supercapacitor integrated device according to claim 1 , wherein the thermoelectric unit body of the thermoelectric power generation module comprises a thermoelectric channel interposed between the two heat sources and composed of an n-type or p-type semiconductor, and

wherein each of the plurality of supercapacitor modules further comprises a dielectric layer interposed between the pair of collector electrodes and the thermoelectric channel composed of the n-type semiconductor.

11. The thermoelectric supercapacitor integrated device according to claim 10 , wherein each of the plurality of supercapacitor modules comprises an rGO (reduced graphene oxide) active electrode disposed between the thermoelectric channel composed of the n-type semiconductor and the dielectric layer.

Assignments (1)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Nov 1, 2018
From: KIM, SANG SIG; CHO, KYOUNG AH; YANG, KYUNG WHAN
To: KOREA UNIVERSITY RESEARCH AND BUSINESS FOUNDATION
Reel/Frame 047383/0153 →
Priority Claims (1)
KR 10-2018-0012419 · Jan 31, 2018 · national
Continuity (1)
Related Publication 20190237509A1 · Aug 1, 2019