Interposer for connecting an antenna on an IC substrate to a dielectric waveguide through an interface waveguide located within an interposer block
An interposer that acts as a buffer zone between a transceiver IC and a dielectric waveguide interconnect is used to establish two well defined reference planes that can be optimized independently. The interposer includes a block of material having a first interface region to interface with an antenna coupled to an integrated circuit (IC) and a second interface region to interface to the dielectric waveguide. An interface waveguide is formed by a defined region positioned within the block of material between the first interface region and the second interface region.
1. An interposer comprising:
a block of material having parallel first and second surfaces on opposite sides of the block, the block including:
a first interface region on the first surface adapted to be coupled to a first antenna of an integrated circuit (IC) substrate;
a second interface region on the second surface adapted to be coupled to a dielectric waveguide (DWG);
a first interface waveguide formed by a first region within the block between the first interface region and the second interface region;
a third interface region adapted to be coupled to a second antenna of the IC substrate; and
a second interface waveguide formed by a second region within the block between the third interface region and the second interface region and connected to the first interface waveguide.
2. An interposer comprising:
a block of material having parallel first and second surfaces on opposite sides of the block, the block including:
a first interface region on the first surface adapted to be coupled to an antenna of an integrated circuit (IC) substrate;
a second interface region on the second surface adapted to be coupled to a dielectric waveguide (DWG);
an interface waveguide formed by a region within the block between the first interface region and the second interface region; and
a standoff portion configured to support the interposer on the IC substrate.
3. The interposer of claim 2 , wherein the standoff portion surrounds the first interface region and forms a cavity configured to enclose the IC substrate.
4. An interposer comprising:
a block of material having parallel first and second surfaces on opposite sides of the block, the block including:
a first interface region on the first surface adapted to be coupled to an antenna of an integrated circuit (IC) substrate;
a second interface region on the second surface adapted to be coupled to a dielectric waveguide (DWG); and
an interface waveguide formed by an opening through the block between the first interface region and the second interface region.
5. The interposer of claim 4 , wherein the opening is coated with a conductive material.
6. The interposer of claim 4 , wherein the opening is filled with a dielectric material.
7. An interposer comprising:
a block of material including:
a first interface region adapted to be coupled to an antenna of an integrated circuit (IC) substrate;
a second interface region adapted to be coupled to a dielectric waveguide (DWG); and
an interface waveguide formed by a photonic bandgap structure within the block between the first interface region and the second interface region.
8. The interposer of claim 7 , wherein the interface waveguide has a rectangular cross section sized to match a linearly polarized radio frequency signal emitted by the antenna.
9. The interposer of claim 7 , wherein the DWG is mated to the second interface region.
10. An interposer comprising:
a block of material having parallel first and second surfaces on opposite sides of the block, the block including:
a first interface region on the first surface adapted to be coupled to a first antenna of an integrated circuit (IC) substrate;
a second interface region on the second surface adapted to be coupled to a first dielectric waveguide (DWG);
a first interface waveguide formed by a first region within the block between the first interface region and the second interface region;
a third interface region on the first surface adapted to be coupled to a second antenna of the IC substrate;
a fourth interface region on the second surface adapted to be coupled to a second DWG; and
a second interface waveguide formed by a second region within the block between the third interface region and the fourth interface region.
11. The interposer of claim 10 , further comprising a compliant material between the first interface region and the third interface region, in which the compliant material is reflective or absorptive to a radio frequency signal emitted by the first antenna or the second antenna.
12. The interposer of claim 10 , further comprising an electronic bandgap structure between the first interface region and the third interface region.
13. The interposer of claim 10 , wherein:
the first DWG is mated to the second interface region; and
the second DWG is mated to the fourth interface region.
14. An interposer comprising:
a block of material having parallel first and second surfaces on opposite sides of the block, the block including:
a first interface region on the first surface adapted to be coupled to an antenna of an integrated circuit (IC) substrate;
a second interface region on the second surface adapted to be coupled to a dielectric waveguide (DWG); and
an interface waveguide formed by a region within the block between the first interface region and the second interface region, the interface waveguide having a circular cross section sized to match a circularly polarized radio frequency signal emitted by the antenna.
15. A system comprising:
a substrate;
an integrated circuit (IC) mounted on the substrate, the IC having an antenna configured to emit or to receive a radio frequency (RF) signal;
an interposer mounted on the substrate, the interposer having parallel first and second surfaces, and the interposer including:
a cavity that encloses the IC;
a first interface region on the first surface configured to interface with the antenna, and a second interface region on the second surface configured to interface to a dielectric waveguide (DWG); and
an interface waveguide formed by a region within the interposer between the first interface region and the second interface region.
16. The system of claim 15 , wherein the IC is a first IC, the antenna is a first antenna, the cavity is a first cavity, the DWG is a first DWG, the interface waveguide is a first interface waveguide, the region within the interposer is a first region within the interposer, and the system further:
a second IC mounted on the substrate, the second IC having a second antenna configured to emit or further receive RF signals; and
the interposer further including:
a second cavity that encloses the second IC;
a third interface region configured to interface with the second antenna;
a fourth interface region configured to interface to a second DWG; and
a second interface waveguide formed by a second region within the interposer between the third interface region and the fourth interface region.
17. The system of claim 15 , wherein the DWG is mated to the second interface region.
18. The system of claim 15 , wherein the IC is a first IC, the interposer is a first interposer, and the system further comprises:
a second IC mounted on the substrate, the second IC having a second antenna configured to emit or further receive RF signals; and
a second interposer enclosing the second IC.