Dynamic noise shaping in a photon counting system

1. A circuit comprising:

a charge sensitive amplifier (CSA) configured to generate an integrated signal in response to an input signal;

a filter coupled to the CSA and configured to receive the integrated signal and an event signal, the filter configured to generate a filtered output signal; and

a comparator coupled to the filter and configured to receive a primary reference voltage signal and generate the event signal.

2. The circuit of claim 1 further comprising a clock generator coupled to the comparator and configured to generate a first trigger signal, a reset signal and a second trigger signal in response to the event signal.

3. The circuit of claim 2 further comprising a noise reduction circuit coupled to the filter and configured to:

receive the filtered output signal and the first trigger signal; and

generate a fine signal.

4. The circuit of claim 3 further comprising an analog to digital converter (ADC) coupled to the noise reduction circuit and configured to generate a count signal in response to the fine signal and the second trigger signal.

5. The circuit of claim 4 , wherein the CSA comprises:

a primary transconductor having:

an inverting terminal configured to receive the input signal;

a non-inverting terminal configured to receive a bias voltage; and

an output terminal configured to generate the integrated signal; and

a feedback capacitor coupled between the inverting terminal and the output terminal of the primary transconductor.

6. The circuit of claim 5 further comprising a reset switch coupled in parallel to the feedback capacitor and configured to reset the CSA when closed by the reset signal.

7. The circuit of claim 3 , wherein the filter comprises:

a capacitor coupled between the CSA and the noise reduction circuit;

a primary resistor coupled to the capacitor; and

a first switch coupled to the primary resistor and a ground terminal, and configured to be closed by an inverse of the event signal.

8. The circuit of claim 3 , wherein the noise reduction circuit further comprises:

a secondary resistor coupled to the filter and configured to receive the filtered output signal; and

a second switch coupled in parallel to the secondary resistor and configured to be opened by the first trigger signal.

9. The circuit of claim 2 , wherein the clock generator is configured to:

generate the first trigger signal after a first delay following the event signal;

generate the second trigger signal after a second delay following the event signal; and

generate the reset signal after a third delay following the event signal.

10. The circuit of claim 7 further comprising:

a third switch coupled to the CSA and the ground terminal, and configured to be closed by the reset signal; and

a fourth switch coupled between the filter and the ground terminal, and configured to be closed by the reset signal.

11. The circuit of claim 1 , wherein:

the input signal is a current signal;

the filter is a high pass filter;

the filtered output signal is a coarse signal; and

the comparator is an active comparator.

12. A method comprising:

integrating an input signal received by a charge sensitive amplifier (CSA) to generate an integrated signal;

filtering the integrated signal in a filter to generate a filtered output signal, the filter configured to receive an event signal; and

comparing the filtered output signal and a primary reference voltage signal to generate the event signal.

13. The method of claim 12 further comprising:

generating a first trigger signal after a first delay following the event signal;

generating a second trigger signal after a second delay following the event signal; and

generating a reset signal after a third delay following the event signal.

14. The method of claim 13 , wherein the first trigger signal, the second trigger signal and the reset signal are generated following a transition of the event signal to a logic high.

15. The method of claim 13 further comprising inactivating the filter through a first switch when the event signal is high.

16. The method of claim 13 further comprising generating a fine signal by a noise reduction circuit in response to the filtered output signal and the first trigger signal.

17. The method of claim 16 further comprising opening a second switch in the noise reduction circuit by the first trigger signal, the second switch coupled between the filter and an analog to digital converter (ADC).

18. The method of claim 17 further comprising generating a count signal by the ADC in response to the fine signal and the second trigger signal.

19. An imaging system comprising:

a gantry configured to receive a patient and rotate at a defined speed;

an x-ray source disposed in the gantry and configured to emit x-rays towards the patient; and

a plurality of detectors configured to receive to receive x-rays attenuated by the patient, at least one detector of the plurality of detectors configured to generate an input signal in response to the received attenuated x-rays, the at least one detector comprising:

a charge sensitive amplifier (CSA) configured to generate an integrated signal in response to the input signal;

a filter coupled to the CSA and configured to receive the integrated signal and an event signal, the filter configured to generate a filtered output signal; and

a comparator coupled to the filter and configured to receive the filtered output signal and a primary reference voltage signal and generate the event signal.

20. The imaging system of claim 19 further comprising a noise reduction circuit coupled to the filter and configured to: receive the filtered output signal and a first trigger signal; and generate a fine signal.

21. The imaging system of claim 20 , wherein the filter comprises:

a capacitor coupled between the CSA and the noise reduction circuit;

a primary resistor coupled to the capacitor; and

a first switch coupled to the primary resistor and a ground terminal, and configured to be closed by an inverse of the event signal.