Variable delay word line enable

1. A memory device, comprising:

an array of memory cells;

a plurality of bit line pairs connected to the memory cells;

a plurality of word lines connected to the memory cells;

a bit line precharge circuit configured to output a precharge signal to a selected bit line pair of the plurality of bit line pairs in response to a clock pulse;

a word line driver configured to select word lines of the array in response to word line enable signals;

a controller configured to:

output the clock pulse to the bit line precharge circuit,

receive a first address corresponding to a first selected word line of the plurality of word lines,

output, in response to receiving the first address, a first word line enable signal to the word line driver to enable the first selected word line of the plurality of word lines, wherein the first word line enable signal is delayed by a first delay time from the clock pulse,

receive a second address corresponding to a second selected word line of the plurality of word lines, and

output a second word line enable signal to enable the second selected word line of the plurality of word lines, wherein the second word line enable signal is delayed by a second delay time from the clock pulse, the second delay time being different than the first delay time.

2. The memory device of claim 1 , wherein the first delay time and the second delay time are determined based on respective the first address and the second address of the first selected word line and the second selected word line.

3. The memory device of claim 1 , wherein the second delay time is shorter than the first delay time, and wherein the second selected word line is farther from the controller than the first selected word line.

4. The memory device of claim 3 , wherein the second address is higher than the first address.

5. The memory device of claim 1 , wherein the first delay time corresponds to a first range of word line addresses, and the second delay time corresponds to a second range of word line addresses.

6. The memory device of claim 5 , wherein the second range of word line addresses is higher than the first range of word line addresses.

7. The memory device of claim 5 , wherein the first range of word line addresses includes a first half of the word line addresses of the memory array, and the second range of word line addresses includes a second half of the word line addresses of the memory array.

8. The memory device of claim 1 , wherein the controller includes a first delay element configured to establish the first delay time and a second delay element configured to establish the second delay time.

9. The memory device of claim 8 , wherein the first delay element and the second delay element each include at least one inverter.

10. The memory device of claim 8 , wherein the controller is configured to establish the first delay time by changing a logic transition of the second word line enable signal.

11. The memory device of claim 1 , wherein the memory cells include SRAM cells.

12. A memory controller, comprising:

a word line driver configured to receive a word line address signal and a word line enable signal;

a variable delay circuit configured to:

receive a clock pulse;

receive a first word line address corresponding to a first word line of a plurality of word lines of a memory array associated with the memory controller;

determine that the first word line address belongs to a first range of addresses corresponding to a first portion of the plurality of word lines;

delay the received clock pulse by a first delay time in response to determining that the first word line address belongs to the first range of addresses;

receive a second word line address corresponding to a second word line of the plurality of word lines;

determine that the second word line address belongs to a second range of addresses corresponding to a second portion of the plurality of word lines;

delay the received clock pulse by a second delay time in response to determining that the second word line address belongs to the second range of addresses, wherein the second delay time is different than the first delay time; and

output the delayed clock pulse signal to the word line driver.

13. The memory controller of claim 12 , wherein:

the second word line address is higher than the first word line address; and

the second delay time is shorter than the first delay time.

14. The memory controller of claim 13 , wherein the second word line is farther from the controller than the first word line.

15. The memory controller of claim 12 , wherein:

the variable delay circuit includes a first delay element configured to delay the received clock pulse by the first delay time;

a first switch receiving an output of the first delay element and configured to output the delayed clock pulse signal in response to the first word line address indicated by the word line address signal;

a second delay element configured to delay the received clock pulse by the second delay time; and

a second switch receiving an output of the second delay element and configured to output the delayed clock pulse signal in response to the second word line address indicated by the word line address signal.

16. The memory controller of claim 15 , wherein the first switch and the second switch include respective a first tri-state inverter and a second tri-state inverter.

17. A method, comprising:

precharging a selected bit line of a plurality of bit lines of an array of memory cells in response to a clock pulse;

receiving a first word line address corresponding to a first selected word line of a plurality of word lines of the array of the memory cells,

determining a first delay time based on the first word line address;

receiving a second word line address corresponding to a second selected word line of the plurality of word lines,

determining a second delay time based on the second word line address, wherein the second delay time is different than the first delay time;

outputting a first word line select signal in response to the clock pulse delayed by the first delay time from the clock pulse; and

outputting a second word line select signal delayed by the second delay time from the clock pulse, the second delay time being different than the first delay time.

18. The method of claim 17 , wherein the second delay time is shorter than the first delay time, and wherein the second word line address is higher than the first word line address.

19. The method of claim 18 , further comprising:

wherein the first word line address corresponds to the first selected word line that is closer to a controller than the selected second word line.

20. The method of claim 17 , further comprising:

dividing the array into a first segment and a second segment;

wherein the first segment includes the first selected word line;

wherein the second segment includes the second selected word line;

wherein the first delay time is determined based on the first segment; and

wherein the second delay time is determined based on the second segment.