High-κ dielectric layer in three-dimensional memory devices and methods for forming the same

1. A three-dimensional (3D) memory device, comprising:

a substrate;

a memory stack comprising:

a first high-κ dielectric layer above the substrate, and

a plurality of interleaved conductor layers and dielectric layers above the first high-κ dielectric layer; and

a semiconductor plug disposed with a lowest surface of the semiconductor plug directly contacting a highest surface of the substrate and in an opening of the first high-κ dielectric layer.

2. The 3D memory device of claim 1 , further comprising a first channel structure extending vertically above the semiconductor plug and through the memory stack, the first channel structure comprising:

a first memory film above the first high-κ dielectric layer and along a sidewall of the first channel structure, said first memory film being in contact with the semiconductor plug.

3. The 3D memory device of claim 2 , further comprising:

a second channel structure extending vertically above the first channel structure and through the memory stack,

a second high-κ dielectric layer disposed between the first channel structure and the second channel structure; and

an inter-deck plug disposed in an opening of the second high-κ dielectric layer.

4. The 3D memory device of claim 3 , further comprising:

a second memory film above the second high-κ dielectric layer and along a sidewall of the second channel structure, said second memory film being in contact with the inter-deck plug.

5. The 3D memory device of claim 3 , wherein each of the first and second high-κ dielectric layers has a dielectric constant κ higher than that of silicon dioxide.

6. The 3D memory device of claim 5 , wherein each of the first and second high-κ dielectric layers comprises one or more of hafnium dioxide, tantalum pentoxide, titanium dioxide, or silicon oxynitride.

7. The 3D memory device of claim 1 , where the semiconductor plug comprises polysilicon.

8. The 3D memory device of claim 3 , wherein at least one of the first and second high-κ dielectric layers is prepared by Atomic Layer Deposition (ALD).

9. The 3D memory device of claim 3 , wherein at least one of the first and second high-κ dielectric layers comprises two or more layers vertically stacked above the substrate, and wherein each of the two or more layers is a high-κ dielectric layer.

10. The 3D memory device of claim 3 , wherein the opening of at least one of the first and second high-κ dielectric layers is etched by wet etching.

11. The 3D memory device of claim 1 , further comprising an insulation layer between the first high-κ dielectric layer and the substrate.

12. The 3D memory device of claim 3 , further comprising an insulation layer between the second high-κ dielectric layer and a lower channel structure.

13. A method for forming a three-dimensional (3D) memory device, comprising:

forming a first dielectric deck on a substrate, said first dielectric deck comprising:

a first high-κ dielectric layer above the substrate; and

a first plurality of interleaved sacrificial layers and dielectric layers above the first high-κ dielectric layer;

forming a first opening in the first dielectric deck extending vertically through the first dielectric deck;

forming a first memory film and a first semiconductor channel in the first opening and along a sidewall of the first opening;

forming a first hole in the first memory film and the first semiconductor channel at the bottom of the first opening, said first hole exposing the first high-κ dielectric layer;

removing a portion of the first high-κ dielectric layer exposed to the first hole;

forming a first semiconductor plug in the first hole with a lowest surface of the semiconductor plug on a highest surface of the substrate;

filling in the first opening with a first filling layer;

forming a channel plug at the upper end of the first opening, said channel plug contacting the first semiconductor channel; and

replacing the sacrificial layers with conductor layers.

14. The method of claim 13 , further comprising:

forming a second dielectric deck over the first dielectric deck, said second dielectric deck comprising:

a second high-κ dielectric layer above the substrate; and

a second plurality of interleaved sacrificial layers and dielectric layers above the second high-κ dielectric layer;

forming a second opening in the second dielectric deck extending vertically through the second dielectric deck;

forming a second memory film and a second semiconductor channel in the second opening and along a sidewall of the second opening;

forming a second hole in the second memory film and the second semiconductor channel at the bottom of the second opening, said second hole exposing the second high-κ dielectric layer;

removing a portion of the second high-κ dielectric layer exposed to the second hole;

forming a second semiconductor plug in the second hole, said second semiconductor plug conjoining the channel plug to form an inter-deck plug;

filling in the second opening with a second filling layer;

forming a third semiconductor plug at the upper end of the second opening; and

replacing the sacrificial layers with conductor layers.

15. The method of claim 14 , wherein each of the first and second high-κ dielectric layers has a dielectric constant κ higher than that of silicon dioxide.

16. The method of claim 13 , wherein the first semiconductor plug is formed directly on the substrate.

17. The method of claim 14 , further comprising:

planarizing a top surface of one or both of the first and second dielectric decks.

18. The method of claim 14 , wherein at least one of the first and second high-κ dielectric layers comprises two or more layers vertically stacked above the substrate, and wherein each of the two or more layers is a high-κ dielectric layer.

19. A three-dimensional (3D) memory device, comprising:

a substrate;

a first memory deck above the substrate comprising a first plurality of interleaved conductor layers and dielectric layers and a first channel structure;

a high-κ dielectric layer above the first memory deck;

a second memory deck above the high-κ dielectric layer comprising a second plurality of interleaved conductor layers and dielectric layers and a second channel structure; and

a semiconductor plug disposed only partially in an opening of the high-κ dielectric layer and between the first memory deck and the second memory deck.

20. The 3D memory device of claim 19 , further comprising:

a first memory film formed in the first channel structure and along a sidewall of the first channel structure; and

a second memory film formed in the second channel structure and along a sidewall of the second channel structure;

wherein the semiconductor plug is electronically connected with both the first memory film and the second memory film.

21. A three-dimensional (3D) memory device, comprising:

a substrate;

a memory stack comprising:

a first high-κ dielectric layer above the substrate, and

a plurality of interleaved conductor layers and dielectric layers above the first high-κ dielectric layer;

a semiconductor plug disposed above the substrate and in an opening of the first high-κ dielectric layer;

a first channel structure extending vertically above the semiconductor plug and through the memory stack, the first channel structure comprising a first memory film above the first high-κ dielectric layer and along a sidewall of the first channel structure, said first memory film being in contact with the semiconductor plug;

a second channel structure extending vertically above the first channel structure and through the memory stack;

a second high-κ dielectric layer disposed between the first channel structure and the second channel structure;

an inter-deck plug disposed in an opening of the second high-κ dielectric layer; and

an insulation layer between the second high-κ dielectric layer and a lower channel structure.