Channel orientation of CMOS gate-all-around field-effect transistor devices for enhanced carrier mobility

1. A semiconductor integrated circuit device, comprising:

a first-type nanosheet field-effect transistor device and a second-type nanosheet field-effect transistor device disposed on a semiconductor substrate;

wherein the first-type nanosheet field-effect transistor device comprises a first nanosheet stack structure comprising a stack of nanosheet channel layers, wherein each nanosheet channel layer of the first nanosheet stack structure comprises a first channel width;

wherein the second-type nanosheet field-effect transistor device comprises a second nanosheet stack structure comprising at least a first stack of nanosheet channel layers and a second stack of nanosheet channel layers, wherein the first and second stacks of nanosheet channel layers are disposed adjacent to and spaced apart from each other, and wherein each nanosheet channel layer of the first and second stacks of nanosheet channel layers comprises a second channel width, which is less than the first channel width;

wherein horizontal surfaces of the nanosheet channel layers of the first and second nanosheet stack structures are aligned with a first crystal plane of the nanosheet channel layers, which provides a greater carrier mobility of a first type of carrier over a second type of carrier; and

wherein vertical surfaces of the nanosheet channel layers of the first and second nanosheet stack structures are aligned with a second crystal plane of the nanosheet channel layers, which provides a greater carrier mobility of the second type of carrier over the first type of carrier.

2. The device of claim 1 , wherein the first-type nanosheet field-effect transistor device comprises a N-type nanosheet field-effect transistor device, wherein the second-type nanosheet field-effect transistor device comprises a P-type nanosheet field-effect transistor device, wherein the first type of carrier comprises electrons, and wherein the second type of carrier comprises holes.

3. The device of claim 1 , wherein the first crystal plane comprises a <100> crystal plane, and wherein the second crystal plane comprises a <110> crystal plane.

4. The device of claim 1 , wherein the nanosheet channel layers of the first and second nanosheet stack structures comprises a same channel length and a same channel thickness.

5. The device of claim 1 , further comprising a common gate structure disposed around the first and second nanosheet stack structures.

6. The device of claim 5 , wherein the common gate structure comprises a high-k dielectric/metal gate structure.

7. The device of claim 5 , wherein the nanosheet channel layers of the first and second nanosheet stack structures comprise crystalline silicon channel layers.

8. The device of claim 5 , wherein the first-type nanosheet field-effect transistor device and the second-type nanosheet field-effect transistor device form a complementary metal-oxide-semiconductor inverter device.

9. The device of claim 1 , wherein the first channel width is in a range of about 50 nm to about 80 nm, and wherein the second channel width is in a range of about 10 nm to about 20 nm.

10. The device of claim 1 , wherein the first and second stacks of nanosheet channel layers of the second nanosheet stack structure are spaced apart from each other by a distance of no less than 10 nm.

11. The device of claim 1 , wherein the first nanosheet stack structure occupies a first footprint area of the semiconductor substrate, wherein the second nanosheet stack structure occupies a second footprint area of the semiconductor substrate, wherein the first and second footprint areas are substantially the same.

12. A method of fabricating a semiconductor integrated circuit device, comprising:

forming a first-type nanosheet field-effect transistor device and a second-type nanosheet field-effect transistor device on a semiconductor substrate;

wherein the first-type nanosheet field-effect transistor device is formed to include a first nanosheet stack structure comprising a stack of nanosheet channel layers, wherein each nanosheet channel layer of the first nanosheet stack structure comprises a first channel width;

wherein the second-type nanosheet field-effect transistor device is formed to include a second nanosheet stack structure comprising at least a first stack of nanosheet channel layers and a second stack of nanosheet channel layers, wherein the first and second stacks of nanosheet channel layers are disposed adjacent to and spaced apart from each other, and wherein each nanosheet channel layer of the first and second stacks of nanosheet channel layers comprises a second channel width, which is less than the first channel width;

wherein horizontal surfaces of the nanosheet channel layers of the first and second nanosheet stack structures are aligned with a first crystal plane of the nanosheet channel layers, which provides a greater carrier mobility of a first type of carrier over a second type of carrier; and

wherein vertical surfaces of the nanosheet channel layers of the first and second nanosheet stack structures are aligned with a second crystal plane of the nanosheet channel layers, which provides a greater carrier mobility of the second type of carrier over the first type of carrier.

13. The method of claim 12 , wherein the first-type nanosheet field-effect transistor device comprises a N-type nanosheet field-effect transistor device, wherein the second-type nanosheet field-effect transistor device comprises a P-type nanosheet field-effect transistor device, wherein the first type of carrier comprises electrons, and wherein the second type of carrier comprises holes.

14. The method of claim 12 , wherein the first crystal plane comprises a <100> crystal plane, and wherein the second crystal plane comprises a <110> crystal plane.

15. A method of fabricating a semiconductor integrated circuit device, comprising:

forming a nanosheet layer stack over a semiconductor substrate;

patterning the nanosheet layer stack to thereby form (i) a first nanosheet stack structure of a first-type nanosheet field-effect transistor device and (ii) a second nanosheet stack structure of a second-type nanosheet field-effect transistor device;

wherein the first nanosheet stack structure comprises a stack of nanosheet channel layers, wherein each nanosheet channel layer of the first nanosheet stack structure comprises a first channel width;

wherein the second nanosheet stack structure comprises at least a first stack of nanosheet channel layers and a second stack of nanosheet channel layers, wherein the first and second stacks of nanosheet channel layers are disposed adjacent to and spaced apart from each other, and wherein each nanosheet channel layer of the first and second stacks of nanosheet channel layers comprises a second channel width, which is less than the first channel width;

wherein horizontal surfaces of the nanosheet channel layers of the first and second nanosheet stack structures are aligned with a first crystal plane of the nanosheet channel layers, which provides a greater carrier mobility of a first type of carrier over a second type of carrier; and

wherein vertical surfaces of the nanosheet channel layers of the first and second nanosheet stack structures are aligned with a second crystal plane of the nanosheet channel layers, which provides a greater carrier mobility of the second type of carrier over the first type of carrier;

forming a common gate structure which surrounds the first and second nanosheet stack structures; and

forming source/drain layers in contact with end portions of the nanosheet channel layers of the first and second nanosheet stack structures.

16. The method of claim 15 , wherein the first-type nanosheet field-effect transistor device comprises a N-type nanosheet field-effect transistor device, wherein the second-type nanosheet field-effect transistor device comprises a P-type nanosheet field-effect transistor device, wherein the first type of carrier comprises electrons, and wherein the second type of carrier comprises holes.

17. The method of claim 15 , wherein the first crystal plane comprises a <100> crystal plane, and wherein the second crystal plane comprises a <110> crystal plane.

18. The method of claim 15 , wherein the common gate structure comprises a high-k dielectric/metal gate structure.

19. The method of claim 15 , wherein the first channel width is in a range of about 50 nm to about 80 nm, and wherein the second channel width is in a range of about 10 nm to about 20 nm.

20. The method of claim 15 , wherein the first nanosheet stack structure occupies a first footprint area of the semiconductor substrate, wherein the second nanosheet stack structure occupies a second footprint area of the semiconductor substrate, wherein the first and second footprint areas are substantially the same.