Method for updating clock synchronization topology, method for determining clock synchronization path, and device

1. A method for determining a clock synchronization path, comprising:

receiving a first packet from a first network element, wherein the first packet requests to determine a first clock synchronization path for the first network element, wherein the first packet indicates that a second clock synchronization path from a clock injection node of the first network to the first network element is faulty, wherein the second clock synchronization path comprises at least one network element not on the first clock synchronization path, wherein the first network element is a network element in a first network, and wherein the first network element has a clock synchronization capability;

determining the first clock synchronization path from the clock injection node to the first network element based on a clock synchronization topology of the first network, wherein the clock synchronization topology of the first network comprises the clock injection node and the first network element; and

sending first instruction information to the first network element instructing to obtain a clock signal from a previous-hop clock synchronization node of the first network element on the first clock synchronization path.

2. The method of claim 1 , further comprising:

receiving a second packet from the first network element, wherein the second packet comprises clock synchronization capability information of the first network element, wherein the clock synchronization capability information of the first network element comprises information about at least one port in the first network element, and wherein the at least one port has the clock synchronization capability; and

updating the clock synchronization topology of the first network based on the clock synchronization capability information of the first network element.

3. The method of claim 2 , wherein an updated clock synchronization topology of the first network comprises the clock injection node, and wherein the method further comprising determining a third clock synchronization path from the clock injection node to the first network element based on the updated clock synchronization topology of the first network.

4. The method of claim 1 , wherein the first packet is a path computation element communication protocol (PCEP) message.

5. A path computation device, comprising:

a non-transitory computer-readable storage medium storing programming instructions; and

a processor coupled to the non-transitory computer-readable storage medium, wherein the programming instructions cause the processor to be configured to:

receive a first packet from a first network element, wherein the first packet requests to determine a first clock synchronization path for the first network element, wherein the first packet indicates that a second clock synchronization path from a clock injection node of the first network to the first network element is faulty, wherein the second clock synchronization path comprises at least one network element not on the first clock synchronization path, wherein the first network element is a network element in a first network, and wherein the first network element has a clock synchronization capability;

determine the first clock synchronization path from the clock injection node to the first network element based on a clock synchronization topology of the first network, wherein the clock synchronization topology of the first network comprises the clock injection node and the first network element; and

send first instruction information to the first network element instructing to obtain a clock signal from a previous-hop clock synchronization node of the first network element on the first clock synchronization path.

6. The device of claim 5 , wherein the programming instructions further cause the processor to be configured to:

receive a second packet from the first network element, wherein the second packet comprises clock synchronization capability information of the first network element, wherein the clock synchronization capability information of the first network element comprises information about at least one port in the first network, and wherein the at least one port has the clock synchronization capability; and

update the clock synchronization topology of the first network based on the clock synchronization capability information of the first network element.

7. The device of claim 6 , wherein an updated clock synchronization topology of the first network comprises the clock injection node, and wherein the programming instructions further cause the processor to be configured to determine a third clock synchronization path from the clock injection node to the first network element based on the updated clock synchronization topology of the first network.

8. A method for determining a clock synchronization path, comprising:

receiving a first packet from a path computation device in a first network, wherein the first packet requests to determine a first clock injection node of the first network;

determining a first edge network device in the first network as the first clock injection node of the first network based on an inter-network clock synchronization topology, wherein the inter-network clock synchronization topology comprises the first edge network device and a second clock injection node of a second network, and wherein the second network is an upstream network of the first network;

determining the clock synchronization path from the second clock injection node to the first clock injection node; and

sending first instruction information to the path computation device.

9. The method of claim 8 , wherein the first packet further comprises an identifier of a third clock injection node of the first network, and wherein the third clock injection node and the first clock injection node are different edge network devices.

10. The method of claim 8 , further comprising:

receiving a second packet from the path computation device in the first network, wherein the second packet comprises clock synchronization capability information of a first network element in the first network, and wherein the clock synchronization capability information of the first network element comprises information about at least one port having a clock synchronization capability in the first network element; and

updating the inter-network clock synchronization topology based on the clock synchronization capability information of the first network element.

11. The method of claim 10 , wherein the first network element comprises the first edge network device in the first network.

12. The method of claim 10 , wherein an updated inter-network clock synchronization topology further comprises a clock injection node of the second network and a second edge network device having a clock synchronization capability in the first network, and wherein the method further comprises determining the clock injection node of the first network based on the updated inter-network clock synchronization topology.

13. The method of claim 8 , wherein the first packet is a path computation element communication protocol (PCEP) message.

14. An inter-network path computation device, comprising:

a non-transitory computer-readable storage medium configured to store programming instructions; and

a processor coupled to the non-transitory computer-readable storage medium, wherein the programming instructions cause the processor to be configured to:

receive a first packet from a path computation device in a first network, wherein the first packet requests to determine a first clock injection node of the first network;

determine a first edge network device in the first network as the first clock injection node of the first network based on an inter-network clock synchronization topology, wherein the inter-network clock synchronization topology comprises the first edge network device and a second clock injection node of a second network, and wherein the second network is an upstream network of the first network;

determine a clock synchronization path from the second clock injection node to the first clock injection node; and

send first instruction information to the path computation device.

15. The device of claim 14 , wherein the first packet further comprises an identifier of a third clock injection node of the first network, and wherein the third clock injection node and the first clock injection node are different edge network devices.

16. The device of claim 14 , wherein the programming instructions further cause the processor to be configured to:

receive a second packet from the path computation device in the first network, wherein the second packet comprises clock synchronization capability information of a first network element in the first network, and wherein the clock synchronization capability information of the first network element comprises information about at least one port having a clock synchronization capability in the first network element; and

update the inter-network clock synchronization topology based on the clock synchronization capability information of the first network element.

17. The device of claim 16 , wherein the first network element comprises a first edge network device in the first network.

18. The device of claim 16 , wherein an updated inter-network clock synchronization topology further comprises a clock injection node of the second network and a second edge network device having a clock synchronization capability in the first network, and wherein the programming instructions further cause the processor to be configured to determine a third clock injection node of the first network based on the updated inter-network clock synchronization topology.