System for configurable error handling

1. A computing system comprising:

an I/O hardware endpoint;

an I/O hardware endpoint controller in communication with the I/O hardware endpoint and to:

detect an error on the I/O hardware endpoint; and

trigger an interrupt associated with the I/O hardware endpoint in response to detected error; and

a processor to execute a runtime component executed by an operating system of the computing system to:

receive the interrupt;

in response to the received interrupt, determine whether the operating system includes a device-specific method associated with the interrupt; and

if it is determined that the operating system includes a device-specific method associated with the interrupt, determine to handle the error using an operating system handler associated with the I/O hardware endpoint; and

if it is determined that the operating system does not include a device-specific method associated with the interrupt:

determine to handle the error using a firmware runtime error handler associated with the I/O hardware endpoint; and

trigger a firmware interrupt associated with the firmware runtime error handler.

2. A computing system according to claim 1 , wherein the interrupt is an Advanced Configuration and Power Interface System Control Interrupt and the runtime component is an Advanced Configuration and Power Interface software driver.

3. A computing system according to claim 2 , wherein the firmware interrupt is a System Management Interrupt and the firmware runtime error handler is a System Management Mode error handler.

4. A computing system according to claim 2 , wherein determination to handle the error using a firmware error handler associated with the I/O hardware endpoint comprises:

identification of an Advanced Configuration and Power Interface Device-Specific Method registered in the operating system and associated with the I/O hardware endpoint and the firmware error handler.

5. A computing system according to claim 1 , the processor further to execute the firmware error handler and, after execution of the firmware error handler, execute an operating system handler associated with the I/O hardware endpoint.

6. A computing system according to claim 1 , wherein the I/O hardware endpoint is a memory device, wherein the I/O hardware endpoint controller is a memory controller within the processor, and wherein the interrupt is triggered in response to writing of error information by the memory controller into one or more Machine-Specific Registers of the processor.

7. A computing system according to claim 1 , wherein the I/O hardware endpoint is a Peripheral Component Interconnect express device, wherein the I/O hardware endpoint controller is a root port controller, and wherein the interrupt is triggered to a root port error handler.

8. A computer-implemented method comprising:

detecting an error on an I/O hardware endpoint;

triggering an operating system interrupt associated with the I/O hardware endpoint in response to detected error;

receiving the interrupt at a runtime component executed by the operating system;

in response to the received interrupt, determining at the runtime component whether the operating system includes a device-specific method associated with the interrupt;

if it is determined that the operating system includes a device-specific method associated with the interrupt, determining to handle the error using an operating system handler associated with the I/O hardware endpoint; and

if it is determined that the operating system does not include a device-specific method associated with the interrupt:

determining to handle the error using a firmware runtime error handler associated with the I/O hardware endpoint; and

triggering a firmware interrupt associated with the firmware runtime error handler.

9. A computer-implemented method according to claim 8 , wherein the interrupt is an Advanced Configuration and Power Interface System Control Interrupt and the runtime component is an Advanced Configuration and Power Interface software driver.

10. A computer-implemented method according to claim 9 , wherein the firmware interrupt is a System Management Interrupt and the firmware runtime error handler is a System Management Mode error handler.

11. A computer-implemented method according to claim 9 , wherein determining to handle the error using a firmware error handler associated with the I/O hardware endpoint comprises:

identifying an Advanced Configuration and Power Interface Device-Specific Method registered in the operating system and associated with the I/O hardware endpoint and the firmware error handler.

12. A computer-implemented method according to claim 8 , further comprising:

executing the firmware error handler; and

executing an operating system handler associated with the I/O hardware endpoint, after execution of the firmware error handler.

13. A computer-implemented method according to claim 8 , wherein the I/O hardware endpoint is a memory device, wherein the I/O hardware endpoint controller is a memory controller, and wherein the interrupt is triggered by a processor in response to writing of error information into one or more Machine-Specific Registers of the processor.

14. A computer-implemented method according to claim 8 , wherein the I/O hardware endpoint is a Peripheral Component Interconnect express device, wherein the I/O hardware endpoint controller is a root port controller, and wherein the interrupt is triggered to a root port error handler.

15. A computing platform providing a runtime architecture comprising:

an I/O hardware endpoint;

an I/O hardware endpoint controller in communication with the I/O hardware endpoint;

an Advanced Configuration and Power Interface System driver runtime component;

one or more Device-Specific Methods associated with the Advanced Configuration and Power Interface System driver runtime component;

a System Management Mode runtime component;

one or more System Management Mode error handlers associated with the System Management Mode runtime component; and

a processor to detect an error on the I/O hardware endpoint and to trigger an interrupt associated with the I/O hardware endpoint in response to detected error,

wherein the Advanced Configuration and Power Interface System driver runtime component is to:

receive the interrupt and, in response to the received interrupt, determine whether the one or more Device-Specific Methods include a Device-Specific Method associated with the received interrupt;

if it is determined that the one or more Device-Specific Methods include a Device-Specific Method associated with the received interrupt, determine to handle the error using a System Management Mode handler associated with the I/O hardware endpoint; and

if it is determined that the one or more Device-Specific Methods do not include a Device-Specific Method associated with the received interrupt:

determine to handle the error using a firmware runtime error handler associated with the I/O hardware endpoint; and

trigger a firmware interrupt associated with the firmware runtime error handler.

16. A computing platform according to claim 15 , wherein the Advanced Configuration and Power Interface System driver runtime component triggers a System Management Interrupt if it is determined to handle the error using a firmware runtime error handler using one of the one or more System Management Mode error handlers.

17. A computing platform according to claim 15 , wherein the determination to handle the error using a firmware error handler associated with the I/O hardware endpoint comprises:

determination that one of the Advanced Configuration and Power Interface Device-Specific Methods is associated with the I/O hardware endpoint and one of the one or more System Management Mode error handlers.

18. A computing platform according to claim 17 , the processor further to execute the one of the one or more System Management Mode error handlers and, after execution of the one of the one or more System Management Mode error handlers, execute an operating system handler associated with the I/O hardware endpoint.

19. A computing platform according to claim 15 , wherein the I/O hardware endpoint is a memory device, wherein the I/O hardware endpoint controller is a memory controller within the processor, and wherein the interrupt is triggered in response to writing of error information by the memory controller into one or more Machine-Specific Registers of the processor.

20. A computing platform according to claim 15 , wherein the I/O hardware endpoint is a Peripheral Component Interconnect express device, wherein the I/O hardware endpoint controller is a root port controller, and wherein the interrupt is triggered to a root port error handler.