Content addressable memory circuits with threshold switching memristors
A content addressable memory (CAM) structure is provided. The CAM comprises a plurality of CAM cells communicatively coupled to processing circuitry. A plurality of threshold switching (TS) memristors are included, each configured to connect to a one of the plurality of CAM cells, with the first end connected to the CAM cell and the second connected to a match line. A discharge transistor is included and configured to discharge any charge on the match line in response to the CAM receiving a command to perform a search.
1. A content addressable memory (CAM) comprising:
a processing circuitry;
an array of a plurality of CAM cells communicatively coupled to the processing circuitry;
a plurality of threshold switching (TS) memristors, at least one TS memristor configured to connect to each of the plurality of CAM cells;
each TS memristor comprising one of a diffusive memristor, a metal-insulator transition (MIT) device, a Zener diode, a mixed ionic-electronic conducting (MIEC) device;
each of the TS memristors comprising a first end connected to a CAM cell of the plurality of CAM cells and a second end connected to a match line; and
a discharge transistor connected to the match line, the discharge transistor configured to discharge any charge on the match line in response to the CAM receiving a command to perform a search.
2. The CAM of claim 1 , wherein the CAM is configured as one of a binary CAM, a ternary CAM, an analog CAM, a static random access memory (SRAM) CAM.
3. The CAM of claim 1 , further comprising a control circuitry to perform one or more operations of write, read, or search the plurality of CAM cells.
4. The CAM of claim 3 , the control circuitry configured to perform a search operation in response to receiving an instruction from the processing circuitry.
5. The CAM of claim 1 , wherein each CAM cell of the plurality of CAM cells is connected to two TS memristors.
6. The CAM of claim 1 , each TS memristor configured to switch from an OFF state to an ON state when a voltage across a respective TS memristor exceeds a threshold voltage of the respective TS memristor.
7. The CAM of claim 1 , wherein each TS memristor is further configured to switch from an ON state to an OFF state when a voltage across the respective TS memristor falls below a hold threshold.
8. The CAM of claim 1 , each CAM cell comprising:
a first memristor connected in series to a second memristor, wherein:
a first end of the first memristor is connected to a first CAM cell switching transistor;
a first end of the second memristor is connected to a second CAM cell switching transistor; and
a second end of the first memristor and a second end of the second memristor are connected together at a common node;
wherein a TS memristor is connected between the common node and the match line and configured to switch from an OFF state to an ON state when a voltage on the common node exceeds a threshold voltage of the TS memristor.
9. A device comprising:
a processing circuitry;
a communications circuitry communicatively coupled to the processing circuitry;
a content addressable memory (CAM) communicatively coupled to the processing circuitry and the communications circuitry, the CAM comprising:
an array of a plurality of CAM cells communicatively coupled to a control circuitry of the CAM;
a plurality of threshold switching (TS) memristors, at least one TS memristor configured to connect to each of the plurality of CAM cells;
each TS memristor comprising one of a diffusive memristor, a metal-insulator transition (MIT) device, a Zener diode, a mixed ionic-electronic conducting (MIEC) device;
each of the TS memristors comprising a first end connected to a CAM cell of the plurality of CAM cells and a second end connected to a match line; and
a discharge transistor connected to the match line, the discharge transistor configured to discharge any charge on the match line in response to the CAM receiving a command to perform a search.
10. The device of claim 9 , wherein the CAM is configured as one of a binary CAM, a ternary CAM, an analog CAM, a static random access memory (SRAM) CAM.
11. The device of claim 9 , wherein the control circuitry configured to perform a search operation in response to receiving an instruction from the processing circuitry.
12. The device of claim 9 , wherein each TS memristor configured to switch from an OFF state to an ON state when a voltage across a respective TS memristor exceeds a threshold voltage of the respective TS memristor.
13. The device of claim 9 , wherein each TS memristor is further configured to switch from an ON state to an OFF state when a voltage across the respective TS memristor falls below a hold threshold.
14. The device of claim 9 , each CAM cell comprising:
a first memristor connected in series to a second memristor, wherein:
a first end of the first memristor is connected to a first CAM cell switching transistor;
a first end of the second memristor is connected to a second CAM cell switching transistor; and
a second end of the first memristor and a second end of the second memristor are connected together at a common node;
wherein a TS memristor is connected between the common node and the match line and configured to switch from an OFF state to an ON state when a voltage on the common node exceeds a threshold voltage of the TS memristor.
15. The device of claim 9 , each CAM cell comprising:
a high side comprising:
a first memristor having a first end connected to a high data line and a second end connected to a high-side common node;
a first switching transistor having a first side connected to a low data line and a second side connected to the high-side common ground; and
a first TS memristor having a first end connected to a match line and a second end connected to the high-side common node;
a low side comprising:
a second memristor having a first end connected to the high data line and a second end connected to a low-side common node;
a second switching transistor having a first side connected to the low data line and a second side connected to the low-side common ground; and
a second TS memristor having a first end connected to the match line and a second end connected to the low-side common node.
16. A content addressable memory (CAM) comprising:
an array of a plurality of CAM cells, each CAM cell comprising:
a high side comprising:
a first memristor having a first end connected to a high data line and a second end connected to a high-side common node;
a first switching transistor having a first side connected to a low data line and a second side connected to the high-side common ground; and
a first TS memristor having a first end connected to a match line and a second end connected to the high-side common node;
a low side comprising:
a second memristor having a first end connected to the high data line and a second end connected to a low-side common node;
a second switching transistor having a first side connected to the low data line and a second side connected to the low-side common ground; and
a second TS memristor having a first end connected to the match line and a second end connected to the low-side common node; and
a discharge transistor connected to the match line, the discharge transistor configured to discharge any charge on the match line in response to the CAM receiving a command to perform a search.
17. The CAM of claim 16 , wherein each TS memristor comprise one of a diffusive memristor, a metal-insulator transition (MIT) device, a Zener diode, a mixed ionic-electronic conducting (MIEC) device.
18. The CAM of claim 16 , each TS memristor configured to switch from an OFF state to an ON state when a voltage across a respective TS memristor exceeds a threshold voltage of the respective TS memristor.
19. The device of claim 9 , wherein each CAM cell of the plurality of CAM cells is connected to two TS memristors.
20. The CAM of claim 16 , wherein each CAM cell of the plurality of CAM cells is connected to two TS memristors.