Differentiable content addressable memory
Embodiments of the disclosure provide a system, method, or computer readable medium for providing a differentiable content addressable memory (aCAM) that implements an analog input analog storage and analog output learning memory. The analog output of the differentiable CAM can provide input to a learning algorithm, which may compute the gradients in comparison to historic values and reduce data inaccuracies and power consumption.
1. A differential content addressable memory (dCAM) array comprising:
a plurality of rows and columns of dCAM cells, wherein each row of dCAM cells include a high match line and a low match line;
a sense circuit electrically connected to the high match line and low match line, wherein the sensing circuit comprises:
a transimpedance amplifier (TIA) configured to sense a match line current on the low match line, and
an analog to digital converter (ADC) configured to sense an output voltage of the TIA and a match line voltage of the high match line; and
a digital to analog converter (DAC), electrically connected to each column of dCAM cells.
2. The dCAM array of claim 1 , wherein the DAC is configured to apply an aggregated data line input voltage to each column of dCAM cells.
3. The dCAM array of claim 1 , wherein the sense circuit is configured to sense the match line voltage, the match line current, and a sensing voltage.
4. The dCAM array of claim 1 , further comprising:
a plurality of transistors comprising a first transistor and a second transistor electronically connected to the high match line and the low match line, wherein the TIA is configured to sense a discharge current through the first transistor and the second transistor via the match line current on the low match line.
5. The dCAM array of claim 4 , further comprising:
an aggregated data line electrically connected to a third transistor and a fourth transistor, wherein a drain of the third transistor is electrically connected to a gate of the first transistor, wherein a drain of the fourth transistor is electrically connected to a gate of a fifth transistor, and the drain of the fourth transistor is electrically connected to a gate of a sixth transistor, and wherein a source of the sixth transistor and a drain of the fifth transistor are coupled to a gate of the second transistor.
6. The dCAM array of claim 5 , wherein the third transistor and fourth transistor are electrically connected to a high search line and a low search line.
7. The dCAM array of claim 6 , wherein the fifth transistor is electrically connected to the low search line, and the sixth transistor is electrically connected to the high search line.
8. The dCAM array of claim 7 , wherein the drain of the fifth transistor is electrically connected to the drain of the sixth transistor.
9. The dCAM array of claim 7 , wherein the sense circuit further comprises:
a sense amplifier electrically connected to the high match line, wherein the sense amplifier is configured to sense the match line voltage of the high match line and a sensing voltage.
10. The dCAM array of claim 9 , wherein the TIA and ADC can be configured to be turned off during a training operation, and wherein the sense amplifier is further configured to sense the match line voltage on the high match line once the TIA and ADC are turned off.
11. A sense circuit comprising:
a training component comprising:
an analog to digital converter (ADC) electrically connected to a transimpedance amplifier (TIA), wherein the ADC is electrically connected to a first match line, wherein the TIA is electrically connected to a second match line, wherein the TIA is configured to sense a current of the second match line and return an output voltage to the ADC, and wherein the ADC is configured to sense the output voltage of the TIA and a first match line voltage of the first match line; and
an operational component comprising:
a sense amplifier electrically connected to the first match line, wherein the sense amplifier is configured to sense the first match line voltage and a sensing voltage during a training operation.
12. The sense circuit of claim 11 , wherein the TIA and ADC can be configured to be turned off during the training operation.
13. The sense circuit of claim 12 , wherein the sense amplifier is further configured to sense the first match line voltage once the TIA and ADC are turned off.
14. The sense circuit of claim 13 , wherein the sense amplifier is further configured to compare the first match line voltage to the sensing voltage to determine a binary output value.
15. The sense circuit of claim 11 , wherein the ADC is configured to use the output voltage and the first match line voltage to learn a pattern.
16. A method comprising:
sensing, by a transimpedance amplifier (TIA), a current of a second match line of a sense circuit, the sense circuit comprising an analog to digital converter (ADC) electrically connected to the TIA, wherein the ADC is electrically connected to a first match line and the TIA is electrically connected to the second match line;
converting, by the TIA, the current to an output voltage;
sensing, by the ADC from the TIA, the output voltage and a first match line voltage of the first match line;
sense, by a sense amplifier of the sense circuit, a the first match line voltage and a sensing voltage; and
training a differentiable content addressable memory (dCAM) model based on the output voltage and the sensing voltage.
17. The method of claim 16 , further comprising:
turning off the TIA and ADC during the training.
18. The method of claim 17 , wherein the sense amplifier senses the first match line voltage once the TIA and ADC are turned off.
19. The method of claim 18 , further comprising:
comparing, at the sense amplifier, the first match line voltage to the sensing voltage; and
determining a binary output value based on the comparison.
20. The method of claim 16 , further comprising:
learning, by the ADC, a pattern from the output voltage and the first match line voltage.