Systems and methods for efficient matrix multiplication
Disclosed are systems and methods for performing efficient vector-matrix multiplication using a sparsely-connected conductance matrix and analog mixed signal (AMS) techniques. Metal electrodes are sparsely connected using coaxial nanowires. Each electrode can be used as an input/output node or neuron in a neural network layer. Neural network synapses are created by random connections provided by coaxial nanowires. A subset of the metal electrodes can be used to receive a vector of input voltages and the complementary subset of the metal electrodes can be used to read output currents. The output currents are the result of vector-matrix multiplication of the vector of input voltages with the sparsely-connected matrix of conductances.
1. A system of sparse vector-matrix multiplication comprising:
a circuit layer;
a plurality of electrodes on the circuit layer; and
a mesh on and sparsely coupled to the plurality of electrodes, the mesh comprising a plurality of nanowires forming an irregular network, wherein the circuit layer is configured to:
receive a first plurality of input signals;
write a second plurality of input signals on an input set of the plurality of electrodes;
read from an output set of the plurality of electrodes a first plurality of output signals; and
output a second plurality of output signals.
2. The system of claim 1 , wherein the plurality of nanowires comprises of coaxial nanowires having a conductive core wrapped in two-terminal non-volatile memory (NVM) material.
3. The system of claim 2 , wherein the non-volatile memory material comprises a voltage-controlled resistance material.
4. The system of claim 1 , wherein the first plurality of input signals is the second plurality of input signals.
5. The system of claim 1 , wherein the circuit layer converts the first plurality of input signals to the second plurality of input signals.
6. The system of claim 1 , wherein the first plurality of output signals is the second plurality of output signals.
7. The system of claim 1 , wherein the circuit layer converts the first plurality of output signals to the second plurality of output signals.
8. The system of claim 1 , wherein the circuit layer further comprises a column driver and a row driver configured to selectively provide at least one of biasing voltages and training voltages to at least a portion of the plurality of the electrodes.
9. The system of claim 1 , wherein the plurality of electrodes and the mesh comprise a sparsely coupled matrix of conductances.
10. The system of claim 9 , wherein the matrix of conductances is tunable using one or more of temperature-driven phase-change memory mechanisms, unipolar resistive switching, and bipolar memristive mechanisms.
11. A method of providing a sparse vector-matrix multiplication system, comprising:
providing a circuit layer;
providing a plurality of electrodes on the circuit layer;
providing a plurality of coaxial nanowires forming an irregular network on the plurality of electrodes, the plurality of coaxial nanowires being arranged in a mesh; and
sparsely coupling the plurality of coaxial nanowires to the plurality of electrodes.
12. A method of performing a sparse vector-matrix multiplication, comprising:
receiving at an input set of a plurality of electrodes a plurality of input signals from a circuit layer, the plurality of electrodes being sparsely connected to a plurality of coaxial nanowires on the plurality of electrodes, the plurality of coaxial nanowires forming an irregular network and being arranged in a mesh; and
reading from an output set of the plurality of electrodes a plurality of output signals.
13. The method of claim 12 , wherein the coaxial nanowires comprise a metal core wrapped in two-terminal non-volatile memory (NVM) material.
14. The method of claim 13 , wherein the NVM material comprises one or more of a voltage-controlled resistance, memristor, phase-change material (PCM), and resistive random-access-memory (ReRAM) material.
15. The method of claim 14 further comprising:
selectively providing biasing voltages to at least a portion of the plurality of the plurality of electrodes to enable writing voltages into or reading currents from the plurality of the electrodes.
16. The method of claim 14 , wherein voltage-controlled resistances are at intersections of the plurality of the electrodes and the plurality of coaxial nanowires and the method further comprises selectively providing training voltages to at least a portion of the plurality of the electrodes.
17. The method of claim 12 , wherein the plurality of input signals comprise voltages and the plurality of output signals comprise currents.
18. The method of claim 12 , wherein the input and output sets each comprise half of the electrodes of the plurality of electrodes.
19. A method of performing vector-matrix multiplication, comprising:
receiving at an input set of a plurality of electrodes a plurality of input signals from a circuit layer, the plurality of electrodes being sparsely connected to a plurality of coaxial nanowires on the plurality of electrodes, wherein the coaxial nanowires comprise a metal core wrapped in two-terminal non-volatile memory (NVM) material, wherein the NVM material comprises one or more of a voltage-controlled resistance, memristor, phase-change material (PCM), and resistive random-access-memory (ReRAM) material, wherein voltage-controlled resistances are at intersections of the plurality of the electrodes and the plurality of coaxial nanowires;
selectively providing training voltages to at least a portion of the plurality of the electrodes;
reading from an output set of the plurality of electrodes a plurality of output signals; and
receiving a training signal indicating which electrodes in the plurality of the electrodes are to be applied the training voltages.