Semiconductor devices
A semiconductor device includes a channel layer located on a substrate, the channel layer including a conductive oxide, a gate structure located on the channel layer, the gate structure including a gate electrode and gate spacers located on both sidewalls of the gate electrode, and source and drain regions located on both sides of the gate structure in recess regions having a first height from a top surface of the channel layer. The source and drain regions are configured to apply tensile stress to a portion of the channel layer located under the gate structure.
1. A semiconductor device comprising:
a channel layer located on a substrate, the channel layer comprising a conductive oxide;
a gate structure located on the channel layer, the gate structure comprising a gate electrode and gate spacers located on both sidewalls of the gate electrode; and
source and drain regions located on both sides of the gate structure in recess regions having a first height from a top surface of the channel layer,
wherein the source and drain regions are configured to apply tensile stress to a portion of the channel layer located under the gate structure.
2. The semiconductor device of claim 1 , wherein the conductive oxide comprises at least one of InGaZnO x , InGaSiO x , InSnZnO x (ITZO), InZnO x (IZO), SnO 2 , HfInZnO x (HIZO), and YbGaO 3 (ZnO) 5 (YGZO).
3. The semiconductor device of claim 1 , wherein the conductive oxide comprises a material expressed by formula RAO 3 (MO) m , and
wherein R is at least one of scandium (Sc), ytterbium (Yb), lutetium (Lu), and indium (In), A is at least one of gallium (Ga), aluminum (Al), iron (Fe), and indium (In), M is at least one of zinc (Zn) and magnesium (Mg), and m is an integer.
4. The semiconductor device of claim 1 , wherein each of the source and drain regions comprises at least one of amorphous InO 3 —ZnO (IZO), InGaSiO x , phosphorus (P)-doped silicon, arsenic (As)-doped silicon, phosphorous-doped germanium, and arsenic-doped germanium.
5. The semiconductor device of claim 1 , wherein the gate structure extends in a first direction parallel to a top surface of the substrate,
wherein each of the gate spacers has a first thickness in a second direction perpendicular to the first direction and parallel to the top surface of the substrate, and
wherein a distance between the gate electrode and each of the source and drain regions in the second direction is smaller than the first thickness.
6. The semiconductor device of claim 1 , wherein the gate spacers vertically partially overlap the source and drain regions.
7. The semiconductor device of claim 1 , wherein a boundary between a sidewall and a bottom portion of each of the recess regions has a rounded shape.
8. The semiconductor device of claim 1 , wherein each of the source and drain regions comprises:
a first material layer conformally located on inner walls of the recess regions, the first material layer including impurities at a first concentration; and
a second material layer filling the recess regions on the first material layer, the second material layer including impurities at a second concentration different from the first concentration.
9. The semiconductor device of claim 1 , wherein the maximum width of each of the source and drain regions is at the same level as top surfaces of the source and drain regions in a first direction parallel to a top surface of the substrate.
10. The semiconductor device of claim 1 , wherein each of the source and drain regions comprises a protrusion, which protrudes outward in a first direction parallel to a top surface of the substrate, and
wherein the maximum width in the first direction of each of the source and drain regions is at a level that is lower than top surfaces of the source and drain regions and higher than bottom surfaces of the source and drain regions.
11. The semiconductor device of claim 1 , wherein each of the source and drain regions comprises:
an upper region having a first width in a first direction parallel to a top surface of the substrate; and
a lower region located under the upper region, the lower region having a second width smaller than the first width in the first direction.
12. The semiconductor device of claim 1 , wherein the gate structure further comprises a gate insulating layer located between the gate electrode and the channel layer and between the gate electrode and the gate spacers,
wherein the gate electrode comprises at least one of a metal, a metal nitride, and a metal carbide, and
wherein the gate electrode is configured to apply tensile stress to a portion of the channel layer located under the gate structure.
13. The semiconductor device of claim 1 , further comprising:
a capping layer located on the source and drain regions; and
a contact plug located on the capping layer,
wherein the capping layer comprises at least one of phosphorus-doped silicon, arsenic-doped silicon, phosphorus-doped germanium, arsenic-doped germanium, doped indium zinc oxide (InZnO), and indium arsenide (InAs).
14. The semiconductor device of claim 1 , wherein the channel layer has a first lattice constant and each of the source and drain regions includes a material layer having a second lattice constant lower than the first lattice constant.
15. The semiconductor device of claim 1 , further comprising:
an insulating layer located between the substrate and the channel layer,
wherein the insulating layer includes at least one of silicon oxide, silicon nitride, and aluminum oxide.
16. A semiconductor device comprising:
a channel layer located on a substrate, the channel layer comprising a conductive oxide;
a gate structure located on the channel layer, the gate structure comprising a gate electrode and gate spacers located on both sides of the gate electrode; and
source and drain regions located on both sides of the gate structure in recess regions having a first height from a top surface of the channel layer,
wherein the source and drain regions partially overlap the gate spacers in a direction perpendicular to a top surface of the substrate.
17. The semiconductor device of claim 16 , wherein the gate structure extends in a first direction parallel to a top surface of the substrate,
wherein each of the gate spacers has a first thickness in a second direction perpendicular to the first direction and parallel to the top surface of the substrate, and
wherein a distance between the gate electrode and each of the source and drain regions in the second direction is smaller than the first thickness.
18. The semiconductor device of claim 16 , wherein each of the source and drain regions comprises a compressively strained material, and
wherein the source and drain regions are configured to apply tensile stress to a portion of the channel layer located under the gate structure.
19. A semiconductor device comprising:
a channel layer located on a substrate;
a gate structure located on the channel layer, the gate structure comprising gate spacers located on both sidewalls of the gate electrode; and
source and drain regions located on both sides of the gate structure in recess regions having a first height from a top surface of the channel layer, the source and drain regions being configured to apply tensile stress to a portion of the channel layer located under the gate structure,
wherein the channel layer comprises a material expressed by formula RAO 3 (MO) m ,
wherein R is at least one of scandium (Sc), ytterbium (Yb), lutetium (Lu), and indium (In), A is at least one of gallium (Ga), aluminum (Al), iron (Fe), and indium (In), M is at least one of zinc (Zn) and magnesium (Mg), and m is an integer.
20. The semiconductor device of claim 19 , further comprising:
a capping layer located on the source and drain regions; and
a contact plug located on the capping layer,
wherein the capping layer comprises a compressively strained material, and
wherein the capping layer comprises at least one of phosphorus-doped silicon, arsenic-doped silicon, phosphorus-doped germanium, arsenic-doped germanium, doped indium zinc oxide (InZnO), and indium arsenide (InAs).