Memory module with buffered memory packages

1. A memory module operable in a computer system to communicate with a system memory controller via a command/address bus and a data bus, comprising:

a register device configurable to receive input command/address signals from the system memory controller via the command/address bus and to output control signals in response to the input command/address signals, the control signals including buffered command/address signals and data path control signals; and

a plurality of DRAM packages, each respective DRAM package comprising:

terminals including control terminals coupled to the register device and data terminals to be coupled to a respective section of the data bus, the control terminals including first control terminals and second control terminals;

stacked array dies; and

a control die coupled between the stacked array dies and the terminals of the respective DRAM package, the control die including data buffers and a data path control circuit; and

wherein the control die is configurable to:

receive the buffered command/address signals via the first control terminals and the data path control signals via the second control terminals;

provide at least some of the buffered command/address signals to the stacked array dies, including providing respective chip-select signals to respective array dies of the stacked array dies; and

control the data buffers in response to the data path control signals to buffer data signals communicated between a selected array die of the stacked array dies and the respective section of the data bus, the selected array die having received one of the chip select signals that is different from any of the other ones of the chip select signals.

2. The memory module of claim 1 , wherein the register device is configurable to decode the input command/address signals and to generate the data path control signals in accordance with the input command/address signals.

3. The memory module of claim 1 , wherein the data buffers are configurable to selectively isolate one or more array dies of the stacked array dies.

4. The memory module of claim 1 , wherein the control die does not secondarily buffer the buffered command/address signals.

5. The memory module of claim 1 , wherein the data path control circuit is configurable to control a command/address time slot for the buffered command/address signals passing through the control die.

6. The memory module of claim 1 , wherein the data path control circuit is configurable to control a data bus time slot for the data signals.

7. The memory module of claim 1 , wherein the buffered command/address signals include more chip select signals than the input command/address signals.

8. The memory module of claim 1 , further comprising die interconnects including first die interconnects coupled to the data buffers and second die interconnects coupled to the control terminals, each of the first die interconnects being coupled to one or more of the stacked array dies.

9. The memory module of claim 8 , wherein the data buffers include drivers coupled to respective ones of the first die interconnects, the drivers including a first driver coupled to one or more first array dies via a first die interconnect and a second driver and coupled to one or more second array dies via a second die interconnect, the first driver having a first driver size corresponding to a first capacitive load associated with the one or more first array dies and the first die interconnect, the second driver having a second driver size corresponding to a second capacitive load associated with the one or more second array dies and the second die interconnect.

10. A memory module operable in a computer system to communicate with a system memory controller via a command/address bus and a data bus, comprising:

a register device configurable to receive input command/address signals from the system memory controller via the command/address bus, to buffer the input command/address signals, and to output control signals in response to the input command/address signals, the control signals including buffered command/address signals; and

a plurality of DRAM packages, each respective DRAM package comprising:

terminals including control terminals coupled to the register device and data terminals to be coupled to a respective section of the data bus, the control terminals including first control terminals and second control terminals;

stacked array dies; and

a control die coupled between the stacked array dies and the terminals of the respective DRAM package, the control die including data buffers and a data path control circuit; and

wherein the memory module is operable in any one of a plurality of modes including a first mode and a second mode;

wherein, during the first mode, the register device is configurable to generate data path control signals in response to receiving the input command/address signals, the control signals further include the data path control signals, and the control die is configurable to:

receive the buffered command/address signals via the first control terminals and the data path control signals via the second control terminals; and

provide at least some of the buffered command/address signals to the stacked array dies, including providing respective chip-select signals to respective array dies of the stacked array dies;

wherein, during the second mode, the control die is configurable to:

receive the buffered command/address signals via the first control terminals;

generate data path control signals in response to the buffered command/address signals; and

provide secondarily buffered command/address signals to the stacked array dies, including providing respective chip-select signals to respective array dies of the stacked array dies; and

wherein, during the first mode or the second mode, the data path control circuit is configured to control the data buffers in response to the data path control signals to buffer data signals communicated between a selected array die of the stacked array dies and the respective section of the data bus, the selected array die having received one of the chip select signals that is different from any of the other ones of the chip select signals.

11. The memory module of claim 10 , wherein, during the second mode, the control die is configurable to generate data path control signals after decoding the buffered command/address signals.

12. The memory module of claim 11 , wherein the secondarily buffered command/address signals include more chip select signals than the buffered command/address signals.

13. The memory module of claim 10 , wherein the data buffers are configurable to selectively isolate one or more array dies of the stacked array dies.

14. The memory module of claim 10 , wherein, during the first mode, the control die does not buffer at least some of the buffered command/address signals.

15. The memory module of claim 10 , wherein the data path control circuit is configurable to control a command/address time slot for the buffered command/address signals passing through the control die.

16. The memory module of claim 10 , wherein the data path control circuit is configurable to control a data bus time slot for the data signals.

17. The memory module of claim 10 , further comprising die interconnects including first die interconnects coupled to the data buffers and second die interconnects coupled to the control terminals, each of the first die interconnects being coupled to one or more of the stacked array dies.

18. The memory module of claim 17 , wherein the data buffers include drivers coupled to respective ones of the first die interconnects, the drivers including a first driver coupled to one or more first array dies via a first die interconnect among the first die interconnects and a second driver and coupled to one or more second array dies via a second die interconnect among the first die interconnects, the first driver having a first driver size corresponding to a first capacitive load associated with the one or more first array dies and the first die interconnect, the second driver having a second driver size corresponding to a second capacitive load associated with the one or more second array dies and the second die interconnect.

19. The memory module of claim 10 , wherein the control die does not receive data path control signals from the register device via the second control terminals during the second mode.

20. The memory module of claim 10 , wherein, during the first mode, the register device is configurable to perform rank multiplication, and wherein, during the second mode, the control die is configurable to perform rank multiplication.