Semiconductor device with linerless contacts
Semiconductor devices and methods for forming semiconductor devices include opening at least one contact via through a sacrificial material down to contacts. Sides of the at least one contact via are lined by selectively depositing a barrier on the sacrificial material, the barrier extending along sidewalls of the at least one contact via from a top surface of the sacrificial material down to a bottom surface of the sacrificial material proximal to the contacts such that the contacts remain exposed. A conductive material is deposited in the at least one contact via down to the contacts to form stacked contacts having the hard mask on sides thereof. The sacrificial material is removed.
1. A method for forming stacked contacts on a semiconductor device, the method comprising:
opening at least one contact via through a sacrificial material and a dielectric capping layer between the semiconductor device and the sacrificial material down to contacts to expose the contacts;
lining sides of the at least one contact via by selectively depositing a barrier on the sacrificial material selective to the dielectric capping layer and the contacts, such that the barrier covers the sidewalls of the at least one contact via from a top surface of the sacrificial material to a top edge of the dielectric capping layer, such that at least a portion of the dielectric capping layer and the contacts remain exposed;
depositing a conductive material in the at least one contact via down to the contacts to form stacked contacts having the barrier on sides thereof; and
removing the sacrificial material.
2. The method as recited in claim 1 , further including depositing the sacrificial material over the semiconductor device.
3. The method as recited in claim 1 , further including patterning a mask over the sacrificial material to pattern the at least one contact via.
4. The method as recited in claim 1 , further including replacing the sacrificial material by depositing an interlevel dielectric around the at least one contact.
5. The method as recited in claim 4 , wherein depositing the interlevel dielectric including conformally depositing a dielectric material until an upper portion of the dielectric material pinches off to form an air gap below the upper portion.
6. The method as recited in claim 1 , further including planarizing the barrier to remove horizontal portions of the barrier from a surface of the sacrificial material opposite to the semiconductor device.
7. The method as recited in claim 1 , wherein the barrier includes a nitride.
8. A method for forming stacked contacts on a semiconductor device, the method comprising:
forming a dielectric capping layer on the semiconductor device;
forming a sacrificial material on the dielectric capping layer over the semiconductor device;
patterning a mask over the sacrificial material;
opening at least one contact via through the sacrificial material and the dielectric capping layer between the semiconductor device and the sacrificial material down to contacts according to the mask;
lining sides of the at least one contact via by selectively depositing a barrier on the sacrificial material selective to the dielectric capping layer and the contacts, such that the barrier covers the sidewalls of the at least one contact via from a top surface of the sacrificial material to a top edge of the dielectric capping layer, such that at least a portion of the dielectric capping layer and the contacts remain exposed;
depositing a conductive material on the barrier and sidewalls of the dielectric capping layer in the at least one contact via down to the contacts to form stacked contacts having the barrier on a portion of sides thereof;
removing the sacrificial material; and
forming an interlevel dielectric around the stacked contacts.
9. The method as recited in claim 8 , wherein depositing the interlevel dielectric including conformally depositing a dielectric material until an upper portion of the dielectric material pinches off to four an air gap below the upper portion.
10. The method as recited in claim 8 , further including planarizing the barrier to remove horizontal portions of the barrier from a surface of the sacrificial material opposite to the semiconductor device.
11. The method as recited in claim 8 , wherein the barrier includes a nitride.