Power distribution networks for monolithic three-dimensional semiconductor integrated circuit devices
Devices and methods are provided for fabricating monolithic three-dimensional semiconductor integrated circuit devices which include power distribution networks that are implemented with power distribution planes disposed below a stack of device tiers, in between device tiers, and/or above the device tiers to distribute positive and negative power supply voltage to field-effect transistor devices of the device tiers.
1. A device comprising:
a backside layer comprising a first power distribution plane;
a first device tier disposed over the backside layer, wherein the first device tier comprises an integrated circuit comprising field-effect transistor devices;
at least one vertical interconnect structure which vertically connects a source/drain region of at least one field-effect transistor device of the first device tier to the first power distribution plane;
a second device tier disposed over the first device tier, wherein the second device tier comprises an integrated circuit comprising field-effect transistor devices;
a back-end-of-line layer disposed over the second device tier, and
an interconnect structure which extends from the back-end-of-line layer through the second device tier and the first device tier and which contacts the first power distribution plane to connect at least one of positive power supply voltage and negative power supply voltage to the first power distribution plane;
wherein the back-end-of-line layer comprises a second power distribution plane to distribute at least one of positive power supply voltage and negative power supply voltage to the field-effect transistor devices of the second device tier.
2. The device of claim 1 , wherein the first power distribution plane comprises at least one metallic plate, wherein the at least one vertical interconnect structure comprises an interlayer via which provides a direct vertical connection from the source/drain region of the at least one field-effect transistor device of the first device tier to the at least one metallic plate of the first power distribution plane.
3. The device of claim 1 , wherein the first power distribution plane comprises a plurality of parallel wires, wherein the at least one vertical interconnect structure comprises an interlayer via which provides a direct vertical connection from the source/drain region of the at least one field-effect transistor device of the first device tier to at least one of the plurality of parallel wires.
4. The device of claim 1 , wherein the first power distribution plane is configured to distribute negative power supply voltage to the field-effect transistor devices of the first device tier, and wherein the second power distribution plane is configured to distribute positive power supply voltage to the field-effect transistor devices of the second device tier.
5. The device of claim 1 , wherein the first power distribution plane is configured to distribute positive power supply voltage to the field-effect transistor devices of the first device tier, and wherein the second power distribution plane is configured to distribute negative power supply voltage to the field-effect transistor devices of the second device tier.
6. The device of claim 1 , wherein the second power distribution plane comprises a metallic plate and a plurality of contact pads which are isolated from the metallic plate by insulating spacers surrounding the contact pads.
7. The device of claim 6 , wherein the vertical interconnect structure which extends from the back-end-of-line layer through the first and second device tiers, and in contact with the first power distribution plane, is formed, in part, by at least one of the contact pads of the second power distribution plane.
8. The device of claim 1 , wherein the second power distribution plane comprises a plurality of parallel wires.
9. The device of claim 1 , further comprising an inter-tier power distribution plane disposed between the first and second device tiers.
10. The device of claim 9 , wherein the inter-tier power distribution plane comprises a metallic plate and a plurality of contact pads which are isolated from the metallic plate by insulating spacers surrounding the contact pads.
11. A device comprising:
a first device tier, wherein the first device tier comprises an integrated circuit comprising field-effect transistor devices;
a second device tier disposed over the first device tier, wherein the second device tier comprises an integrated circuit comprising field-effect transistor devices;
an inter-tier power distribution plane disposed between the first and second device tiers;
at least one interlayer via which vertically connects a source/drain region of at least one field-effect transistor device of the second device tier to the inter-tier power distribution plane;
a back-end-of-line layer disposed over the second device tier;
a first vertical interconnect structure which extends from the back-end-of-line layer through the second device tier in contact with the inter-tier power distribution plane to connect at least one of positive power supply voltage and negative power supply voltage to the inter-tier power distribution plane;
a backside power distribution plane disposed below the first device tier;
at least one interlayer via which vertically connects a source/drain region of at least one field-effect transistor device of the first device tier to the backside power distribution plane; and
a second vertical interconnect structure which extends from the back-end-of-line layer through the second and first device tiers in contact with the backside power distribution plane to connect at least one of positive power supply voltage and negative power supply voltage to the backside power distribution plane;
wherein the backside power distribution plane comprises a plurality of parallel wires.
12. The device of claim 11 , wherein the inter-tier power distribution plane comprises at least one metallic plate and a plurality of contact pads which are isolated from the metallic plate by insulating spacers surrounding the contact pads, wherein the at least one interlayer via provides a direct vertical connection from the source/drain region of the at least one field-effect transistor device of the second device tier to the at least one metallic plate of the inter-tier power distribution plane.
13. The device of claim 11 , wherein the inter-tier power distribution plane comprises a plurality of parallel wires, wherein the at least one interlayer via provides a direct vertical connection from the source/drain region of the at least one field-effect transistor device of the second device tier to at least one of the plurality of parallel wires.
14. The device of claim 11 , wherein the backside power distribution plane is configured to distribute negative power supply voltage to the field-effect transistor devices of the first device tier, and wherein the inter-tier power distribution plane is configured to distribute positive power supply voltage to the field-effect transistor devices of the second device tier.
15. The device of claim 11 , wherein the backside power distribution plane is configured to distribute positive power supply voltage to the field-effect transistor devices of the first device tier, and wherein the inter-tier power distribution plane is configured to distribute negative power supply voltage to the field-effect transistor devices of the second device tier.
16. The device of claim 11 , wherein the backside power distribution plane comprises a mesh-type pattern which is formed, in part, by the plurality of parallel wires.
17. A device comprising:
a first device tier, wherein the first device tier comprises an integrated circuit comprising field-effect transistor devices;
a second device tier disposed over the first device tier, wherein the second device tier comprises an integrated circuit comprising field-effect transistor devices;
an inter-tier power distribution plane disposed between the first and second device tiers;
at least one interlayer via which vertically connects a source/drain region of at least one field-effect transistor device of the second device tier to the inter-tier power distribution plane;
a back-end-of-line layer disposed over the second device tier;
a first vertical interconnect structure which extends from the back-end-of-line layer through the second device tier in contact with the inter-tier power distribution plane to connect at least one of positive power supply voltage and negative power supply voltage to the inter-tier power distribution plane;
a backside power distribution plane disposed below the first device tier;
at least one interlayer via which vertically connects a source/drain region of at least one field-effect transistor device of the first device tier to the backside power distribution plane; and
a second vertical interconnect structure which extends from the back-end-of-line layer through the second and first device tiers in contact with the backside power distribution plane to connect at least one of positive power supply voltage and negative power supply voltage to the backside power distribution plane;
wherein the backside power distribution plane comprises a stacked structure of two or more backside power distribution planes.
18. The device of claim 17 , wherein the backside power distribution plane is configured to distribute negative power supply voltage to the field-effect transistor devices of the first device tier, and wherein the inter-tier power distribution plane is configured to distribute positive power supply voltage to the field-effect transistor devices of the second device tier.
19. The device of claim 17 , wherein the backside power distribution plane is configured to distribute positive power supply voltage to the field-effect transistor devices of the first device tier, and wherein the inter-tier power distribution plane is configured to distribute negative power supply voltage to the field-effect transistor devices of the second device tier.
20. The device of claim 17 , wherein the backside power distribution plane is configured to distribute both positive power supply voltage and negative power supply voltage to the field-effect transistor devices of the first device tier.