Controlling filament formation and location in a resistive random-access memory device
A method for manufacturing a semiconductor memory device includes forming a bottom electrode on a bottom contact layer, and forming a dielectric layer covering sides of the bottom electrode. In the method, a switching element layer is deposited on the dielectric layer and the bottom electrode, a top electrode layer is deposited on the switching element layer, and a hardmask layer is deposited on the top electrode layer. The switching element, top electrode and hardmask layers are patterned into a pillar on the bottom electrode. The method further includes forming a spacer layer on the dielectric layer on sides of the pillar, and forming a metal layer on the dielectric layer adjacent the spacer layer and around the pillar.
1. A method for manufacturing a semiconductor memory device, comprising:
forming a bottom electrode on a bottom contact layer;
forming a dielectric layer covering sides of the bottom electrode;
depositing a switching element layer on the dielectric layer and the bottom electrode;
depositing a top electrode layer on the switching element layer;
depositing a hardmask layer on the top electrode layer;
patterning the switching element layer, the top electrode layer and the hardmask layer into a pillar on the bottom electrode;
forming a spacer layer on the dielectric layer on sides of the pillar;
forming a metal layer on the dielectric layer adjacent the spacer layer and around the pillar; and
recessing the metal layer to a height less than a height of the pillar.
2. The method according to claim 1 , wherein a width of the pillar is greater than a width of the bottom electrode.
3. The method according to claim 1 , wherein the bottom electrode comprises first and second metal nitride layers deposited by physical vapor deposition (PVD).
4. The method according to claim 3 , wherein the first metal nitride layer comprises tantalum nitride (TaN) and the second metal nitride layer comprises titanium nitride (TiN).
5. The method according to claim 3 , further comprising patterning the first and second metal nitride layers into the bottom electrode.
6. A method for manufacturing a semiconductor memory device, comprising:
forming a bottom electrode on a bottom contact layer;
forming a dielectric layer covering sides of the bottom electrode;
depositing a switching element layer on the dielectric layer and the bottom electrode;
depositing a top electrode layer on the switching element layer;
depositing a hardmask layer on the top electrode layer;
patterning the switching element layer, the top electrode layer and the hardmask layer into a pillar on the bottom electrode;
forming a spacer layer on the dielectric layer on sides of the pillar;
forming a metal layer on the dielectric layer adjacent the spacer layer and around the pillar;
wherein the bottom electrode comprises first and second metal nitride layers deposited by physical vapor deposition (PVD); and
patterning the first and second metal nitride layers into the bottom electrode;
wherein the patterning of the first and second metal nitride layers comprises forming a mask on a portion of the first and second metal nitride layers and removing an unmasked portion of the first and second metal nitride layers.
7. The method according to claim 1 , wherein the dielectric layer is deposited on the bottom electrode by atomic layer deposition.
8. The method according to claim 7 , further comprising planarizing the dielectric layer to expose a top surface of the bottom electrode.
9. The method according to claim 1 , wherein the switching element layer comprises a high-k dielectric.
10. The method according to claim 1 , wherein the top electrode layer comprises a trilayer structure of a first titanium layer, an aluminum layer stacked on the first titanium layer and a second titanium layer stacked on the aluminum layer.
11. The method according to claim 1 , further comprising depositing an inter-layer dielectric layer on the metal layer.
12. The method according to claim 11 , further comprising removing the hardmask layer from the pillar.
13. The method according to claim 12 , further comprising forming a top contact layer on the top electrode layer of the pillar.