Resistive RAM cell structure for gradual set programming
A method is presented for enabling heat dissipation in resistive random access memory (RRAM) devices. The method includes forming a plurality of conductive lines within an interlayer dielectric (ILD) and forming a RRAM stack over a conductive line of the plurality of conductive lines, the RRAM stack including a bottom electrode, a conductive pillar, thermal conducting layers, and a top electrode. The thermal conducting layers are disposed on opposed ends of the conductive pillar. The thermal conducting layers directly contact the top electrode and the bottom electrode. The thermal conducting layers include aluminum oxide (Al 2 O 3 ).
1. A method for enabling heat dissipation in resistive random access memory (RRAM) devices, the method comprising:
forming a plurality of conductive lines within an interlayer dielectric (ILD); and
forming a RRAM stack over a conductive line of the plurality of conductive lines, the RRAM stack including a bottom electrode, a conductive pillar, thermal conducting layers, and a top electrode, wherein the thermal conducting layers occupy an entirety of a space defined between the top and bottom electrodes.
2. The method of claim 1 , wherein the bottom electrode directly contacts the conductive line.
3. The method of claim 1 , wherein the thermal conducting layers are disposed on opposed ends of the conductive pillar.
4. The method of claim 1 , wherein the thermal conducting layers directly contact the top electrode and the bottom electrode.
5. The method of claim 1 , wherein the thermal conducting layers include aluminum oxide (Al 2 O 3 ).
6. The method of claim 1 , wherein the conductive pillar directly contacts the top electrode and the bottom electrode.
7. The method of claim 1 , wherein the conductive pillar is a hafnium oxide pillar.
8. The method of claim 1 , wherein a via is formed over the conductive line to expose the top electrode of the RRAM stack, the via filled with a conductive material.
9. A method for enabling heat dissipation in resistive random access memory (RRAM) devices, the method comprising:
forming a plurality of conductive lines within an interlayer dielectric (ILD);
forming a bottom electrode over a conductive line of the plurality of conductive lines;
depositing a thermal conducting layer over the bottom electrode;
depositing a diblock co-polymer layer over the thermal conducting layer, the diblock co-polymer layer annealed to induce phase separation;
selectively removing one phase from the phase separation;
patterning the thermal conducting layer to create vias therein; and
filling the vias with a conductive material to define conductive pillars, the conductive pillars formed from and including a single material.
10. The method of claim 9 , further comprising removing the conductive pillars such that a conductive region remains over the bottom electrode and thermal conducting regions remain adjacent the conductive region.
11. The method of claim 10 , wherein the conductive region remaining over the bottom electrode has a substantially T-shaped configuration.
12. The method of claim 11 , wherein the conductive region having the substantially T-shaped configuration is etched to form a single conductive pillar adjacent the thermal conducting regions.
13. The method of claim 12 , further comprising depositing a top electrode over the single conductive pillar and the thermal conducting regions.
14. The method of claim 13 , wherein the bottom electrode directly contacts the conductive line.
15. The method of claim 14 , wherein the thermal conducting regions are disposed on opposed ends of the single conductive pillar.
16. The method of claim 15 , wherein the thermal conducting regions directly contact the top electrode and the bottom electrode.
17. The method of claim 15 , wherein the thermal conducting regions include aluminum oxide (Al 2 O 3 ).
18. The method of claim 15 , wherein the single conductive pillar directly contacts the top electrode and the bottom electrode, the single conductive pillar being a hafnium oxide pillar.
19. A semiconductor structure for enabling heat dissipation in resistive random access memory (RRAM) devices, the semiconductor structure comprising:
a plurality of conductive lines disposed within an interlayer dielectric (ILD);
a bottom electrode disposed in direct contact with a conductive line of the plurality of conductive lines;
an electrically conductive pillar disposed in direct contact with the bottom electrode;
thermal conducting regions disposed in direct contact with the bottom electrode, the electrically conductive pillar confined between the thermal conducting regions; and
a top electrode disposed in direct contact with the electrically conductive pillar and the thermal conducting regions.
20. The semiconductor structure of claim 19 , wherein the thermal conducting regions include aluminum oxide (Al 2 O 3 ) and the electrically conductive pillar includes hafnium oxide.