Instruction for determining histograms
A processor is described having a functional unit of an instruction execution pipeline. The functional unit has comparison bank circuitry and adder circuitry. The comparison bank circuitry is to compare one or more elements of a first input vector against an element of a second input vector. The adder circuitry is coupled to the comparison bank circuitry to add the number of elements of the second input vector that match a value of the first input vector on an element by element basis of the first input vector.
1. A system comprising:
a system memory to store instructions and data; and
a processor, coupled to the system memory, comprising:
a decoder to decode a histogram instruction to perform histogram binning operations,
a processor storage to store a first plurality of data elements to be processed by the histogram instruction,
at least one packed data register to store a second plurality of data elements, each data element of the second plurality of data elements to store a count associated with a histogram bin, and
execution circuitry to perform histogram binning operations responsive to the histogram instruction, the execution circuitry comprising:
bin selection circuitry to select one of the second plurality of data elements responsive to a value of each of the first plurality of data elements, and
bin update circuitry to increase the count in each of the second plurality of data elements selected by the bin selection circuitry.
2. The system of claim 1 , further comprising a storage device coupled to the processor to store instructions and data.
3. The system of claim 1 , further comprising an input/output (I/O) interconnect to couple the processor to one or more I/O devices.
4. The system of claim 1 , wherein the system memory comprises a dynamic random access (DRAM) memory.
5. The system of claim 1 , further comprising a graphics processor coupled to the processor to perform graphics processing operations.
6. The system of claim 1 , further comprising a network processor coupled to the processor.
7. The system of claim 1 , further comprising an audio input/output device coupled to the processor.
8. The system of claim 1 , wherein the bin update circuitry is to update one or more of the second plurality of data elements corresponding to one or more histogram bins identified by the bin selection circuitry.
9. The system of claim 1 , wherein the bin update circuitry comprises circuitry to increment a value of the one or more of the second plurality of data elements corresponding to one or more histogram bins identified by the bin selection circuitry.
10. The system of claim 1 , further comprising a memory unit having a translation lookaside buffer (TLB) to cache virtual to physical address translations.
11. The system of claim 1 , wherein the histogram instruction comprises an extension to an instruction set architecture (ISA).
12. The system of claim 1 , wherein the execution circuitry is in a vector unit of the processor.
13. The system of claim 1 , wherein the bin update circuitry comprises an adder circuit.
14. A method comprising:
storing instructions and data into a system memory of a system;
decoding a histogram instruction to perform histogram binning operations into a decoded histogram instruction with a decoder of a processor of the system;
storing a first plurality of data elements to be processed by the histogram instruction in a processor storage of the processor; and
executing the decoded histogram instruction to perform histogram binning operations with execution circuitry comprising:
bin selection circuitry selecting one of a second plurality of data elements in at least one packed data register of the processor responsive to a value of each of the first plurality of data elements, each data element of the second plurality of data elements to store a count associated with a histogram bin, and
bin update circuitry increasing the count in each of the second plurality of data elements selected by the bin selection circuitry.
15. The method of claim 14 , wherein the bin update circuitry increases the count in each of the second plurality of data elements by one when selected by the bin selection circuitry.
16. The method of claim 14 , wherein the at least one packed data register comprises a plurality of packed data registers and the second plurality of data elements comprise packed data elements, each packed data element associated with a different histogram bin.
17. The method of claim 16 , wherein each packed data register comprises a 512-bit data register and each of the second plurality of data elements comprises a 16-bit data element.
18. The method of claim 14 , wherein the first plurality of data elements are loaded from the system memory to the processor storage.
19. The method of claim 18 , wherein the processor storage comprises a cache memory.
20. The method of claim 14 , wherein the bin update circuitry comprises an adder circuit increasing the count.
21. A system comprising:
a system memory to store instructions and data; and
a processor, coupled to the system memory, comprising:
a decoder to decode a histogram instruction to perform histogram binning operations,
a processor storage to store a first plurality of data elements to be processed by the histogram instruction,
at least one packed data register to store a second plurality of data elements, each data element of the second plurality of data elements to store a count associated with a histogram bin, and
execution circuitry to perform histogram binning operations responsive to the histogram instruction, the execution circuitry comprising:
means to select one of the second plurality of data elements responsive to a value of each of the first plurality of data elements, and
means to increase the count in each of the second plurality of data elements selected by the means to select one of the second plurality of data elements.