Memory system and nonvolatile memory

1. A memory system comprising:

a nonvolatile memory including a plurality of memory cells at intersection locations of a plurality of stacked word lines and a memory pillar passing through the plurality of word lines in a stacking direction, the plurality of word lines including a first group of word lines stacked above a second group of word lines in the stacking direction; and

a controller configured to read data of a first memory cell in a first read mode and to read data of a second memory cell in a second read mode different from the first read mode, wherein

the first memory cell is at an intersection location of a word line that is in a boundary area of the first and second groups of word lines and the memory pillar, and the second memory cell is at an intersection location of a word line that is not located in the boundary area, wherein

the boundary area that includes the word line is adjacent to a location of the memory pillar where a width of the memory pillar in a direction perpendicular to the stacking direction of the memory pillar discontinuously changes along the stacking direction.

2. The memory system according to claim 1 , wherein

the first read mode is a read mode that compensates for an influence from a memory cell that is adjacent to the first memory cell along the memory pillar.

3. The memory system according to claim 2 , wherein

the second read mode is one of a normal read mode and a fast read mode.

4. The memory system according to claim 1 , wherein

the controller is configured to perform a retry sequence when error correction of data read from the first memory cell fails, and to read the data of the first memory cell in the first read mode in a first read operation of the retry sequence.

5. The memory system according to claim 1 , wherein

the controller is configured to read the data of the first memory cell in the second read mode in a first read operation, and to read the data of the first memory cell in the first read mode in a retry read operation that is performed when error correction of the data read in the first read operation fails.

6. The memory system according to claim 5 , wherein

the controller is further configured to retrieve information on reliability of data stored in the first memory cell, and

when the information on reliability of data stored in the first memory cell indicates a first reliability level, the controller reads the data of the first memory cell in the second read mode in a retry read operation, and when information on reliability of the data stored in the first memory cell indicates a second reliability level lower than the first reliability level, the controller reads the data of the first memory cell in the first read mode in the retry read operation.

7. The memory system according to claim 6 , wherein

the information on reliability of the data stored in the first memory cell includes at least one of a bit error ratio detected in the error correction of the data read from the first memory cell, a retry rate of a read operation performed on the first memory cell, and a number of read operations performed on a block of memory cells including the first memory cell since the first memory cell has been programmed.

8. The memory system according to claim 1 , wherein

the controller is further configured to retrieve information on reliability of data stored in the first memory cell, and,

when the information on reliability of data stored in the first memory cell indicates a first reliability level, the controller reads the data of the first memory cell in the second read mode in a first read operation, and when the information on reliability of the data stored in the first memory cell indicates a second reliability level lower than the first reliability level, the controller reads the data of the first memory cell in the first read mode in the first read operation.

9. The memory system according to claim 1 , wherein

the first memory cell is configured to store a plurality of bits including a first bit and a second bit, and

the controller is configured to read data of the first bit in the first memory cell in the first read mode, and read data of the second bit in the first memory cell in the second read mode.

10. The memory system according to claim 1 , wherein

the boundary area includes one word line.

11. The memory system according to claim 1 , wherein

the boundary area includes two or more word lines.

12. The memory system according to claim 1 , wherein

the boundary area includes a word line adjacent to a boundary of a first tier of the memory pillar and a second tier of the memory pillar on top of which the first tier of the memory pillar is stacked.

13. The memory system according to claim 12 , wherein

the boundary area further includes an area including a word line corresponding to a lower end of the second tier.

14. The memory system according to claim 12 , wherein

the boundary area further includes an area including a word line corresponding to an upper end of the first tier.

15. The memory system according to claim 1 , wherein

the first memory cell is located at an intersection location of a first word line and the memory pillar, and the second memory cell is located at an intersection location of a second word line and the memory pillar, and

the first and second word lines are separated by at least two word lines.

16. A nonvolatile memory device comprising:

a memory cell array including a plurality of memory cells at intersection locations of a plurality of stacked word lines and a memory pillar passing through the plurality of word lines in a stacking direction, the plurality of word lines including a first group of word lines stacked above a second group of word lines in the stacking direction; and

a control circuit configured to read data of a first memory cell in a first read mode and to read data of a second memory cell in a second read mode different from the first read mode in response to a command sequence including a sense command and an automatic read mode selection command, wherein

the first memory cell is at an intersection location of a word line that is in a boundary area of the first and second groups of word lines and the memory pillar, and the second memory cell is at an intersection location of a word line that is not located in the boundary area, wherein

the boundary area that includes the word line is adjacent to a location of the memory pillar where a width of the memory pillar in a direction perpendicular to the stacking direction of the memory pillar discontinuously changes along the stacking direction.

17. The nonvolatile memory device according to claim 16 , wherein

the first memory cell is located at an intersection location of a first word line and the memory pillar, and the second memory cell is located at an intersection location of a second word line and the memory pillar, and

the first and second word lines are separated by at least two word lines.

18. A method of performing a read operation on a nonvolatile memory including a memory cell array the memory cell array, including a plurality of memory cells at intersection locations of a plurality of stacked word lines and a memory pillar passing through the plurality of word lines in a stacking direction, the plurality of word lines including a first group of word lines stacked above a second group of word lines in the stacking direction, said method comprising:

reading data of a first memory cell in a first read mode and reading data of a second memory cell in a second read mode different from the first read mode by sending a command sequence including a sense command and an automatic read mode selection command to the nonvolatile memory, wherein

the first memory cell is at an intersection location of a word line that is in a boundary area of the first and second groups of word lines and the memory pillar, and the second memory cell is at an intersection location of a word line that is not located in the boundary area, wherein

the boundary area that includes the word line is adjacent to a location of the memory pillar where a width of the memory pillar in a direction perpendicular to the stacking direction of the memory pillar discontinuously changes along the stacking direction.

19. The method according to claim 18 , wherein

the first memory cell is located at an intersection location of a first word line and the memory pillar, and the second memory cell is located at an intersection location of a second word line and the memory pillar, and

the first and second word lines are separated by at least two word lines.