Semiconductor device and manufacture thereof
A semiconductor device and its manufacturing method are presented. The manufacturing method includes: providing a semiconductor structure comprising: an interlayer dielectric layer, a first metal layer surrounded by the interlayer dielectric layer, and a semiconductor layer on the interlayer dielectric layer; etching the semiconductor layer to form an opening exposing the interlayer dielectric layer, wherein the opening comprises a first opening and a second opening on the first opening; forming an insulation layer on the semiconductor structure; etching the insulation layer and the interlayer dielectric layer at the bottom of the first opening to form a groove exposing a portion of the first metal layer; forming a second metal layer on the insulation layer and on the bottom and a side surface of the groove; and patterning the second metal layer. The second metal layer in this inventive concept can be removed more completely than conventional methods.
1. A semiconductor device manufacturing method, comprising:
providing a semiconductor structure, comprising:
an interlayer dielectric layer;
a first metal layer surrounded by the interlayer dielectric layer; and
a semiconductor layer on the interlayer dielectric layer;
etching the semiconductor layer to form an opening exposing the interlayer dielectric layer, wherein the opening comprises a first opening and a second opening on the first opening, with the first opening exposing a portion of the interlayer dielectric layer, and the first opening and the second opening forming a staircase pattern;
forming an insulation layer on the semiconductor structure;
etching a portion of the insulation layer and a portion of the interlayer dielectric layer at the bottom of the first opening to form a groove exposing a portion of the first metal layer;
forming a second metal layer on the insulation layer and on the bottom and a side surface of the groove, with the second metal layer contacting the first metal layer; and
patterning the second metal layer to remove a portion of the second metal layer on a side surface of the opening and on the staircase pattern,
wherein the insulation layer comprises a first side, a second side, and a third side, wherein the first side is completely positioned inside the second opening and is connected through the second side to the third side, wherein the second side is oblique relative to each of the first side and the third side; wherein the third side directly contacts the second metal layer; and wherein both the first side and the second side are completely exposed by the second metal layer between two opposite portions of the second metal layer after patterning the second metal layer.
2. The method of claim 1 , wherein the width of the second opening is larger than the width of the first opening.
3. The method of claim 1 , wherein an angle between a side surface of the first opening and the bottom of the first opening is an obtuse angle, and an angle between a side surface of the second opening and a flat surface of the staircase pattern is an obtuse angle.
4. The method of claim 1 , wherein an angle between a side surface of the first opening and the bottom of the first opening is in a range of 100° to 110°, and an angle between a side surface of the second opening and a flat surface of the staircase pattern is in a range of 100° to 110°.
5. The method of claim 1 , wherein etching the semiconductor layer to form an opening exposing the interlayer dielectric layer comprises:
forming a patterned first hard mask layer on the semiconductor structure, wherein the first hard mask layer comprises a through-hole exposing a first portion of the semiconductor layer;
etching the semiconductor layer with respect to the first hard mask layer to form a well;
remove a portion of the first hard mask layer to enlarge the through-hole and to expose a second portion of the semiconductor layer near the well;
etching the well and the second portion of the semiconductor structure to form a first opening exposing a portion of the interlayer dielectric layer and a second opening on the first opening; and
removing the first hard mask layer.
6. The method of claim 5 , wherein a portion of the first hard mask layer is removed to enlarge the through-hole by adjusting the concentration of etching gas.
7. The method of claim 6 , wherein the etching gas comprises oxygen.
8. The method of claim 1 , wherein etching a portion of the insulation layer and a portion of the interlayer dielectric layer at the bottom of the first opening to form a groove exposing a portion of the first metal layer comprises:
forming a patterned second hard mask layer on the semiconductor structure after the insulation layer has been formed, with the second hard mask layer exposing a portion of the insulation layer at the bottom of the first opening;
etching the exposed portion of the insulation layer and a portion of the interlayer dielectric layer underneath the insulation layer with respect to the second hard mask layer to form a groove, with the groove exposing a portion of the first metal layer; and
removing the second hard mask layer.
9. The method of claim 1 , wherein patterning the second metal layer to remove a portion of the second metal layer on a side surface of the opening and on the staircase pattern comprises:
forming a patterned third hard mask layer on the second metal layer, with the third hard mask layer exposing a portion of the second metal layer on the side surface of the opening and on the staircase pattern;
etching the exposed portion of the second metal layer with respect to the third hard mask layer; and
removing the third hard mask layer.
10. The method of claim 1 , wherein
the interlayer dielectric layer comprises silicon dioxide, the semiconductor layer comprises silicon, the first metal layer comprises aluminum, the insulation layer comprises silicon dioxide, and the second metal layer comprises aluminum.